Engineer Design

JOHN SCHACHTE

*** ****** ***** *****, ****, NC **513 [H] : 919-***-**** [M] : 919-***-****

Reliable, independent, and effective team player. Principal Design Engineer with 28 years engineering

experience for full-scale development projects with a focus on analysis, modeling, design, design tradeoffs,

implementation, verification, and ability to understand impact of hardware and software changes on reliability,

performance, and clarity from conception to production to customer acceptance. Experienced in writing

complex verilog/system verilog/C/Perl code. Served as project leader of video compression and

decompression development projects used for video guided missiles. Previous experience as project lead of the

hub terminal development for a satellite based communication network. Experienced in the resolution of field

problems working with innovative field and system engineers.

EDUCATION: FLORIDA INSTITUTE OF TECHNOLOGY, Melbourne, Florida 1983-1987

MSEE Electrical Engineering with major in Communications Systems. 3.75/4.0

NORTH CAROLINA STATE UNIVERSITY, Raleigh, North Carolina 1979-1983

BSEE Electrical Engineering. Graduated Cum Laude

EXPERIENCE:

NVIDIA Corporation, contract position based in Santa Clara, CA from OCT/2011 –DEC/2011

ASIC Timing Closure – Performed Timing Closure on 3 partitions for a large 28 nm chip developed by

nVidia. My previous supervisor called to ask if I could help out on a large chip that was under-staffed.

EDAC Medical – Emboli Detection and Classification, Cary, NC from JUN/2011 - Present

Principal Design Engineer

Verilog coded the EDAC ultrasound processor module in an Altera Cyclone series EP2S60 series chip. The

EDAC is used for gaseous and solid detection of non-blood elements in a blood circuit used primarily for

bypass surgeries and dialysis procedures. Design includes Stationary Target Cancellation, Band Pass Filter,

Hilbert Transform, Low Pass Filter, Peak Detection, Slope/Velocity Calculations, an FFT based Classifier and

Tracking Processor. Re-wrote the micro-code (C-based) for the existing Intel 8051 micro-controller.

NVIDIA Corporation, based in Durham, NC from JUL/2002 – JUN/2011

ASIC Design Engineer

Verilog design and verification of the depth processor over 3 generations of the Nvidia generic graphics

processing units. The depth processor involved analyzing compressed depth representations of triangles in a

very complex scheme. Performed final timing closure of over 10 chips of the Nvidia GPU and Tegra product

lines. All design in verilog, verification in C, and timing work with Perl scripts and primarily synopsis tools.

NetOctave, Research Triangle Park, NC from MAR/2001 – JUL/2002

Principal ASIC Design Engineer

Played a key role in developing SSL and IPSEC hardware acceleration chips for a start-up company. Designed

and tested the HMAC, Crypto Controller, Security Association and Policy search engines and DDR-SDRAM

interface modules. The HMAC authenticates IPV4 packets with MD5 or SHA-1 algorithm. The crypto

controller controlled encryption/decryption and authentication of IPV4 packets operating in ESP or AH

protocol. Designs were successfully tested and synthesized using Synopsis/VERA design tools. Design was

synthesized at Phillips Semiconductor for implementation in .18um CMOS with operational speed of

200Mhz.

Volumetrics Medical Imaging, Durham, North Carolina APR/1996 - MAR/2-01

Director of Engineering, APR/99-MAR/01

Served as Project Leader of the next generation multi-channel, 3D beamforming acquisition system for the

real-time Volumetrics Ultrasound machine. Board was modeled with 73 Altera 200k FPGAs emulating eight 3

Mgate ASICs. Potential ASIC vendors under evaluation were NEC, Atmel and Phillips. Final form board

contained 64 x 10-bit ADCs with anti-alias filters as well as 8 ASICs to simultaneously generate 16 receive

beamforms from 64 input transducer channels. Eight boards in cascade with 400Mhz LVDS interconnect to

form 16 receive beamformers from a 512 channel transducer.

Principal Engineer, 4/96-4/99

Worked primarily with 3D beamforming and 3D scan-conversion designs for volumetric ultrasound

acquisition system. Used primary design tools: Altera Flex 10k/10kE series FPGA design and SHARC DSP

processor. Wrote all real-time spectral Doppler processing code in C for blood flow detection and direction

utilizing an Analog Devices SHARC microprocessor. Served as technical lead supplying system guidance on

sensitivity in the analog receiver and ADC sampling areas.

Scientific Atlanta, Atlanta, Georgia (based in Melbourne, Florida) 1991-1996

Senior Staff Engineer

Led the hub station development for a new generation development of VSAT equipment. Designed first digital

burst demodulator in the division and developed the hub PAD board including satellite data link acquisition

circuitry implemented in Xilinx hardware. PAD processor was 68020 based. Served as project lead of another

digital designer and an analog designer during two-year development and integration project. Modeled and

implemented a novel bandwidth spreading implementation allowing the outlink to transmit 6dB more power.

Increased link budget sufficient to reduce typical receive antenna size from 1.8m to 1.2m. Design was given a

U.S. patent.

Harris Corporation, Government Aerospace Systems Division, Melbourne, Florida 1983-1991

Lead Engineer / Branch Leader, 1988-1991 - Security Clearance: Top Secret with EBI

Led numerous R&D projects in spread-spectrum (CDMA) communications: Direct Spread, Frequency

Hopped, TDMA and a novel transform domain LPI communication systems which is patented. Managed up to

10 engineers during this time. Led and designed hardware development (discrete MSI, PLDs, FFTs and Xilinx

FPGAs), DSP code development (mixed Assembly and C with TI TMS 320 series microprocessors), upper

level protocol software and user interface code development (VME Motorola processor board with Ethernet

connection written in C).

Lead Engineer / Group Leader, 1986-1988

Served as full-scale development subtask leader of a $1.1M project which successfully developed a video

compression/decompression system (LSI gate array based) for a spread-spectrum communication system on a

Rockwell International video guided bomb. Served as Project Lead for a successful $900K project which

delivered a spread-spectrum link simulator with video compression/decompression hardware to Rockwell.

Senior Engineer, 1983-1986

Served as Digital Designer in the analog sub-task of a chirp based spread spectrum communication platform

providing better than 1 foot range accuracy through air based triangulation. Digital design for a contrast filter

with 100MHz and 10KH ECL acquisition circuitry. Designed hardware processor which performed total time

uncertainty acquisition, fine-acquisition timing to 2.5nsec and data demodulation (2/8/16-ary PPM). The

100mhz ECL design was converted to an AMCC gate array. Designed a 68000 based processor (hardware and

firmware) providing interpolation of 20+ parameters associated with a fighter jets position and predicted future

position.

AWARDS RECEIVED

Patent Number 6,241,675 Method and Systems for Determining Velocity of Tissue Using Three

Dimensional Ultrasound Data.

Patent Number 5,029,184: Low Probability of Intercept Communication System.

Patent Number 5,454,009: Method and Apparatus for Providing Energy Dispersal using Frequency

Diversity in a Satellite Communication System.

Patent Pending for Intra-Oral X-ray Reception utilizing CCD Technology.

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