Project Design

Seeking a Full-time position in the field of Engineering.

EDUCATION

|University |Degree |Year |GPA/Percentage |

| | |Graduated | |

|UNIVERSITY OF SOUTH |Master of Science in |Dec 2012 |4.0/4.0 |

|ALABAMA, MOBILE, AL, |Electrical Engineering | | |

|ANNA UNIVERSITY, CHENNAI,|Bachelor in Engineering|May 2010 |78% |

|INDIA |in Electronics and | | |

| |Communication | | |

| |Engineering | | |

SKILLS

C, C++, Python, Matlab, ModelSim, Xilinx, Microwind, PSpice, CADENCE-

Composer/Virtuoso, HSpice/Spectre, Extraction tools, Verilog, Allen Bradley

PLC-RXLogix, Silos, PCB design, OrCAD Capture, QCADesigner, Wookie,

Microprocessor 8086 and 68HC11, Arduino programming, and CCNA.

SUMMARY

. Hands-on experience in teaching and helping student in the design

laboratory experiment and troubleshooting issues.

. Excellent knowledge in CMOS-Schematic design, Layout design, Simulation,

Floor planning, Synthesis using CADENCE.

. Excellent knowledge in signal/Image processing using MATLAB.

. Good communication and time management skills, good analytical and

problem solving abilities, self-motivated, punctual, open-minded, team

player, eager to learn new things.

EMPLOYMENT EXPERIENCE

Teaching Assistant- University of South Alabama, Mobile, AL

Jan/2011 - May/2012

. Graded homework, lead laboratory projects, hosted office hours.

. Installed CADENCE and the necessary tools in the university computers.

. Prepared tutorial for Schematics design, symbol design, layout design,

Verilog/VHDL simulation, and floor planning of IC for CADENCE.

. Taught CADENCE for student in EE 534 VLSI design systems.

. Handled CADENCE lab class for student in EE 534 VLSI design systems

. Assisted various classes ranging from EE 227 to EE 565.

System Analyst Intern - Televox, Software, Mobile, AL.

June/2011 - Aug/2011

. Performed daily server checks and maintains.

. Monitored the server activities throughout the day and covered

notification and recovery.

. Deployment of upgrading the SQL 03 to SQL 08 and Microsoft Server 2000 to

2008.

. Analysis research ticket for the task server and application server to

enhance the server capacity.

. Troubleshooting database issues.

. Validated the error in the task server.

ACTIVITIES & AFFLIATIONS

. GRADUATE ASSISTANTSHIP, University of South Alabama - Spring 2012, Fall

2011, Spring 2011

. Member of IEEE, Tau Beta Pi, Eta Kappa Nu, Treasurer in Indian Student

Association 2011

. Participated in the ASIC design Workshop conducted by Open Silicon and

EEA, MIT. (Mar 2010).

PROJECT/THESIS

GRADUATE THESIS

Title : CAD tool for Quantum Dot Cellular Automata (QCA)

Oct 2010 - Present

Tools : QCADesigner, HDLQ, ModelSim, CADENCE, NC-Verilog, Matlab

Description: The crux of the project is to develop a Computer-aided design

(CAD) which performs the design check rule in QCA circuit and automate the

operation need for HDLQ implementation such partition of the QCA circuit

and generation of the HDL code for the QCA circuit using HDLQ library. The

gates are to be designed using the QCADesigner and also verification is to

be done using CADENCE. The CAD tool has been developed using MATLAB.

GRADUATE PROJECT

Course: EE425 Prog Logic Controller Lab

Title : Automation in chemical preparation plant Apr

2011 - May2011

Tool : PLC - RXLogix

Description: The crux of the project is to build a PLC ladder logic using

RXlogix to automate the chemical preparation plant to perform the given

task and to incorporate the emergency safe feature in it.

Course : EE 543 HDL Logic Simulation

Title : Vending Machine Oct 2011 -

Dec 2011

Tool : Silos (Verilog simulator)

Description: Wrote a Verilog code for the task performed by the vending

machine by definite state diagram and test using Silos.

Course : EE 548 Computer Network Security

Title : Hybrid DES April 2011-

May 2011

Tool : MATLAB

Description: By combing important features in both DES and AES and we came

up with an encoding/decoding algorithm which accepts 32 bit input. My

responsibility is to write the MATLAB coding for the algorithm and to

analyze metric and avalanche properties for the developed algorithm.

Course : EE 566 Digital Image Processing

Jan 2011 - May 2011

Title : 1. Experimentation of Two-Dimensional Fourier Transform Operation

2. High Resolution Image Reconstruction using Multiple Low

Resolution Frames

3. Edge Enhancement using Nonlinear Operators for Noise-Free/Noisy

Binary and Gray Level

4. Image Enhancement using Histogram Equalization and Contrast

Stretching

5. Image Restoration via Wiener Filter

6. Pattern Recognition using Classical Joint Transform Correlation

Tool : MATLAB

Description: I was asked to write MATLAB code without using MATLAB function

for all projects, so that I can understand the concept better and to

performance analysis of each project.

Course : EE 534 VLSI Design Systems

Title : 2x4 Decoder layout design Nov 2010 -

Dec 2010

Tool : Microwind

Description: The crux of the project is to design an efficient 2x4 Decoder

in the transistor level using Microwind and to analyze the timing

simulation for all combinational outputs.

UNDERGRADUATE PROJECT

Title : An Efficient FFT Core on a Reconfigurable Architecture

Aug 2009- April 2010

Tools : Mentor Graphic Simulator-ModelSim, Xilinx FPGA

Description : The crux of the project is on designing and implementing a

reconfigurable architecture which can implement the Transform Decomposition

concept. The Functional verification of the new reconfigurable architecture

was done using ModelSim and then the prototyping was done on XILINX FPGA.

This paper was presented at Third National Conference on Digital

Convergence 2010 held on 11th

and 12th April 2010 at R.M.K Engineering College, Tamil Nadu, INDIA.

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