Design Project

SHADAB PERWEZ

[pic] Email: ******.********@*****.***

Ph. no:-+91-843*******

Career objective:

To work in the learning environment where I can utilize my skills and

abilities to deliver my full potential and want to be a part of innovation.

Educational Qualifications:-

|Course |Board/University/Institution |Year of |Percentage |

| | |passing |(approx.) |

|M.S (VLSI &|JNTU Hyderabad |2012 |75% |

|ESD) | | | |

|B.E (ECE) |VCE, Rohtak (MDU University) |2010 |73% |

|12th |CBSE (Patna Muslim High School) |2004 |63% |

|(HSC) | | | |

|10th (SSC)|CBSE (Patna Muslim High School) |2002 |74% |

Subjects of Interest:-

. VLSI.

. Digital Electronics

. Electronics Device Circuit.

. Mathematics.

Languages known:-

C, Verilog and Perl.

Tools Exposed to:-

VCS, Design Compiler and IC Compiler

Experience:-

Two years of teaching assistantship at JNTU Hyderabad

Technical Projects:-

Project 1:-

Title: - Peripheral Component Interconnect

Description: PCI (Peripheral Component Interconnect) is a computer

bus for attaching hardware devices in a computer. We write the Verilog

code of different module of PCI. And to observe the simulation results

according to PCI protocol using VCS.

Tools Used- VCS

Project 2:-

Title: - Design for Testability (DFT)

Description: Take a design (I2C Slave) and run through the steps of DFT.

After setting the design constraints we perform for the scan style. And if

the design rule is met we build scan chains. It gives the optimized net

list with scan. We again check constrain and design rules and saved the

design for testing.

While doing the project I understand the basic of Design for Testability.

Tools used: - Design Compiler, DFT compiler.

Project 3:-

Title: PCI parity checker

Description: We generate SERR# and PERR# error signal from PCI parity

checker based on PCI protocol. Understand the behavior of PCI parity

checker by reducing from RTL to gate level net list using DC compiler and

SAED_90nm library and observe physical design flow up to routing using IC

compiler.

Tools Used: - VCS, DC compiler and IC compiler.

Project4:-

Title:-Standard Cell Memory Design

Description: Writing a Verilog code for 32K*4 SRAM. While designing the

SRAM we design a 3*8 decoder and a SR latch using custom design. The

outputs of the decoder and SR latch are verified using custom designer.

Later in the projects we use the same decoder and SR latch and verified the

output of SRAM. The outputs of the SRAM using Verilog and the outputs of

SRAM using Custom design are matched.

While doing the project we understand the memory arrangement and its

working.

Tools Used: Custom Designer, VCS

Project5:-

Title: Mechanical model of RJ11

Description: We have given a jack named RJ11 and the task is to design a

similar mechanical model of RJ11 with hand. While doing the project we

understand that there is very low yield rate during manufacturing. We

understand that there are a lot of issues to take care of regarding the

specification of the component during manufacturing.

Project 6:

Title: Design of Analog to Digital Converter using Custom Designer.

Description: We have design an analog to digital converter by designing

different components of ADC like OP-AMP, Comparator, and multiplexer using

custom designer. Then design analog to digital converter using these entire

component and verify its accuracy rate.

Tools used- Custom Designer

Project 7:- (B.E eight Semester)

Title: - Speed and direction control of Stepper Motor uses Microcontroller

Description: Motor has step angle of 1.8 /pulse. To rotate motor shaft for

one complete revolution, it requires 200 pulses to drive motor circuits.

Step pulse is digitally counted & stop when desired number of pulses is

achieved which is digitally controlled by a programmable controller.

Extra Activities:-

. Secured third position in moving making in TECHNO FUN FEST.

. Work as a coordinator in TECHNO FUN FEST.

. Qualifying NATIONAL TALENT SEARCH EXAMINATION at SSC level.

Strengths:-

. Good communication skills.

. Able to debug error and good problem solving ability.

. Giving maximum efforts to my work and self driven.

. Hard working, disciplined and honest.

Personnel Profile:-

Date of birth : 02nd January 1988.

Sex : Male

Father's name : Mr. Pervez Hassan

Marital Status : Single

Nationality : Indian.

Hobbies : Playing cricket and teaching.

Languages known : Hindi, English and Urdu.

Permanent Address : P.O: Mahendru, P.S: Sultangunj, Patna-800006,

Bihar, India.

Declaration:

I hereby declare that all the details mentioned above are true to the best

of my knowledge

Date: 12-12-2012

Place: Patna SHADAB PERWEZ

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