Engineer Engineering

Phaneendra Raguru Mobile: +91-779*******

E Mail: **********.******@*****.***

: **********.******@*******.***

Objective:

To expertise in designing of VLSI circuits & chips and to achieve organization goals.

Technical Strength:

ASIC Design.

FPGA Emulation using Verilog and VHSIC Hardware Description Language.

Embedded system design.

Technical Skill-Set:

Hardware Languages : Verilog, VHDL, System Verilog, Basics of OVM and UVM.

Cadence tool : Virtuoso Schematic Editor, Analog Environment, Virtuoso

Layout Editor, SOC Encounter.

Simulators : PSpice, Modelsim, Tanner, Quartus, LTSpice, Xilinx ISE,

Vivado.

Programming and Scripting : UNIX Shell scripts, SQL, Python, Basic PERL, Basic Tcl, C,

C++, JAVA.

Operating Systems : UNIX, Linux, Windows.

Embedded Platform : 8086, 8051, Intel Atom Development Kit.

Education:

QUALIFICATI NAME OF THE BOARD/ YEAR AGGREGATE

ON INSTITUTION UNIVERSITY OF / CGPA

NAME PASSING

IIIT – H

M.Tech ( VLSI (Deemed 2014 9.94

and Computer University)

Engineering)

B. Tech RAJEEV GANDHI Jawaharlal Nehru 2012 82.37 %

(Electronics and MEMORIAL Technological

Communication COLLEGE, University,

Engineering) NANDYAL Anantapur.

Intermediate Nalanda jr college, Board Of 2008 97 %

Nandyal. Intermediate

Education

X class Keshava Reddy EM Board Of 2006 90.86 %

SCHOOL, Nandyal. Secondary

Education

Work Experience

Vitesse Semiconductors, Hyderabad, Validation Engineer Jan 2014 ( 1 Year )

Implemented 256 bit MACSec Encryption AES-GCM on FPGA with and without

pipelined Architecture.

Performing MACSEC System Validation on Malibu 10G PHY.

Research Experience, IIIT Hyderabad:

M.Tech Thesis:

Tape-out of Phase Locked Loop for HDMI Applications at 3.4GHz using Cadence.

Description:

A 3.4 GHz Phase Locked Loop ( PLL ) with a Differential Ring oscillator based VCO

is fabricated in a 180-nm technology CMOS process with 1.8V power supply. The reference

clock frequency is 212.5 MHz with a mod 16 frequency divider. The PLL can be locked from

2.539GHz to 5.0793GHz with a lock range of 2.54GHz with 48.58% of duty cycle. PLL

consumes 10.18 mA current and 18.32 mW power.

Projects:

“Emergency alert system using GPS and GSM" using Intel Atom Development kit.

Extended Double Precision floating point multiplier using Carry Save Adder using

VHDL.

System Search algorithm in PYTHON.

Shell and LS implementation in C++.

64 bit high speed adder using higher valency Trees using Cadence.

Wireless notice board using RF using PCB.

Achievements:

1. Secured Gold Medal with 1st position in M.Tech VLSI and Computer Engineering at

IIIT-H.

2. Secured 1st position in 1st,3rd and 4th semesters of M.Tech at IIIT-H.

3. Secured 1st position consecutively in B.Tech 1st year and 2nd year 1st semester .

4. Secured 2nd position in Xpress2K10 elocution.

5. Presented Phase Locked Loop as an R&D Poster in IIIT Hyderabad.

Extra-Curricular Activities:

1) Organizing Friends for Seva (an NGO), which provides education for poor students.

2) Providing Blood for patients who are in need from voluntary donors and also

conducted blood camp in Govt hosp, Nandyal.

3) Organized Food Contribution programs in and around Nandyal and Hyderabad at

various homes for mentally challenged, old age homes and orphanages.

Declaration:

I hereby declare that the information given above is true.

Phaneendra R

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