SANKEERTH SREESHAN
VIBHOOTHI,
Valavilpeedika,
P.O.Mamba,
Kannur, Kerala
India 670611
abgl6g@r.postjobfree.com
LinkedIn: in.linkedin.com/pub/sankeerth-sreeshan/82/25b/a6/
CAREER OBJECTIVE
Seeking a challenging and rewarding opportunity as a VLSI fresher in design and synthesis of
digital or analog integrated circuits, verification of ASIC designs, FPGA verification and
designing SoC with an organisation of repute which recognize my potential while nurturing
my technical skills.
PROFILE
Pursing All India P.G Diploma in VLSI & Embedded Hardware Design and B.E
in Electronics and Communication Engineering.
Knowledge about Designing and Verification of ASSIC IC’s by VHDL and
Verilog.
Knowledge on Embedded C and product development using Microcontrollers.
Knowledge on FPGA Designing and Prototyping.
TECHNICAL SKILLS
Operating system: Windows 7, XP, Linux.
EDA tools: ModelSim, XILINX, Qurtex, Cadence nc launch, Orcad pspice, Orcad
Layoutplus, Keil μ, Code Composer Studio .
Languages: C, C++, VHDL, Verilog, TCL scripting.
Applications: Microsoft Office Tools.
EDUCATIONAL QUALIFICATION
Pursing All India P.G Diploma in VLSI & Embedded Hardware Design
In 2014 Aug - 2015 Feb from National Institute of Electronics and Information
Technology, Calicut (formerly Doecc).
Qualified B.E. Electronics &Communication Engineering in 2010 – 2014 from
V.S.B Engineering college, Kaur under Anna university,Chennai with a
CGPA: 7.30.
Qualified Higher Secondary from St. Michaels Anglo-Indian Higher Secondary
School, Kannur in 2008-2010 under state board with 70.92%.
Qualified S.S.L.C from St. Michaels Anglo-Indian Higher Secondary School, Kannur
in 2008 under state board with ‘A+’ grade in all the subjects.
IN PLANT TRAINING
Attended a 7 day in plant training at Regional Telecom Training Centre, BSNL,
Chennai in general in plant training.
PROJECTS UNDERTAKEN
DESGN AND DEVELOPMENT OF A MICROSIGNAL PROCESSOR.
(main project P.G.D)
Review: To develop a SoC by interfacing open MSP430 with the DSP / DIP engines
(interfaced with FFT) and to make obtain its GDSII file for fabrication. The designing
include the interfacing of the IPcores of the controller and the peripherals together and its
verification of each individual IPcores and the whole. The development includes the physical
designing, analysing the constrains and development of the GDSII file.
RFID-BASED AUTOMATIC MULTI-LEVEL PARKING SYSTEM. (mini
project P.G.D)
Review: Design and development of automatic multi-level vehicle parking system based on
RFID. It proposes to successfully make the parking automatically, thereby reducing
manpower requirement by using an Atmel 895C2 Microcontroller.
RTL VERIFICATION OF FIFO AND 1024X8 RAM.
Review: To verify the given RTL of a FIFO by using some test benches and different test
case scenarios thereby automate the program and correct the errors.
DESIGN AND SYNTHESIS OF A RISC STORRED-PROGRAM
MACHINE. (mini project P.G.D)
Review: To design and to synthesis a RISC machine by using Verilog which is having
registers, ALU, controller for acting as an RISC_SPM.
FABRICATION OF THIN FILM TRANSISITORFOR DRAM
APPLICATIONS USING ODTS WITH HIGH – κ DIELECTRICS
ZrO2.(B.E.)
Review: To fabricate a thin film transistor for DRAM application with high-κ dielectric
nanomaterial (ZrO2) with κ=25, and organic semiconductor (ODTS) and its results were
studied and found to be in ambipolar nature and the transistor threshold voltage is found to be
very low where its operational voltage is found very low and switching speed is very high.
CABLE TESTER. (B.E.mini-project)
Review: Designed and implemented a cable tester to test the continuity of a cable which is
insulated by sensing the frequency passing through the cable by using an op-amp.
Personal Details
Date of Birth : 24-12-1992
Gender : male
Father name : Sreeshan K
Contact numbers
Marital status : single
Nationality : Indian
Languages Known: Malayalam, English, Hindi (to read and write), and Tamil (to speak)
Hobbies : Watching movies, listing to Music, Reading.
PLACE: CALICUT SIGNATURE
DATE: