Engineer Project Manager
Resume:
DENNIS EDWARD McCARTY
Oakland, CA 94619
*************@*****.***
OBJECTIVE: Permanent or Contract Design or Management Hardware Engineering, Marketing or
Technical Writing.
SKILLS: Twenty-four years Digital System Design, Project Management and Technical Marketing
Extensive experience in FPGA system design (Altera, Xilinx, Actel, Orca)
Development tools: ISE, ModelSim, Quartus
Debuggers: ChipScope, SignalTap, Identify
Design of embedded systems using microprocessors and microcontrollers
Serial/Parallel Interfaces: SONET, Fast/Gig Ethernet, SATA, UTOPIA, POSPHY, PCI,
PCI Express
High-speed PCB Design
Verilog, VHDL RTL, Behavioral Design and Synthesis (Model Tech, Synplicity, Synopsys)
Design simulation models and Test Benches.
Programming languages: C, C++, Java
Excellent oral and written and communication skills
EXPERIENCE:
Siemens TTB 5/11 to 5/2012
Consultant
• Designed packet duplication detection algorithm RTL and test bench in VHDL.
Simulated and implemented system on Altera Stratix 4 FPGA at 125 MHz. Design
inclides RGMII interface and scalable width/depth for source addresss.
• W rote system specification for adding HSR/PRP packet redundancy to industrial
Ethernet switch.
Arasan Chip Systems 12/10 to 6/11
Consultant
• W rite data sheets, training presentations, press releases and user guides for a range
of company Verilog IP products including MIPI standards, SD/SDIO, NAND Flash.
Work with engineers on specifications of new products.
Siemens TTB 3/08 to 12/08
Consultant
• Architected, designed in VHDL, simulated and implemented in Altera Cyclone 3 a
proprietary, hardware spanning tree protocol employing a Marvell Gigabit Ethernet
switch device. The protocol offers extremely fast VLAN ring fault switching. Used
Quartus 2, ModelSim and Signal Tap debugger. Design used State machines, FIFOs,
multiple clocks and SRAM. Wrote test bench and simulated in Model Tech. Debug
with Signal Tap and logic analyzer. Project completed.
M2000 3/07 to 9/07
Consultant
• W rote HW, SW and Tool MRD documents for new FPGA device family. Specified IP
for devices. Specified PCB requirements. Used Mentor Precision to implement test
designs.
Velogix 8/06 to 1/07
Consultant
• W rote, simulated and implemented a design in Verilog on a Xilinx Virtex 5 using to
connect PCI Express, USB and PMC channels to a proprietaty bus. Used a PCI
Express core and test bench for design and simulation. Used PCIE analyzer board.
Project partially completed when company closed.
Synplicity 10/04 to 4/06
Technical Marketing Manager
• Hands-on management of the Identify debugger and Premier synthesis products.
Perform market analysis, write technical articles and papers and prepare product
plans for use with Xilinx V4 and Altera FPGA products.
Nuvation 5/04 to 10/04
Project Manager Consultant
• Designed and implemented a hardware video data processor on Xilinx Virtex 2 Pro
that scaled and multiplexed a BT656 video stream. Included external video buffer
management.
Schlumberger 1/02 to 7/02
Contract Design Engineer
• Specified and designed scan controller for IC inspection and repair system. The
controller was designed in VHDL and included a 100 MBit Ethernet MAC core. It was
implented on an Altera Excalibur FPGA including a processor and memory interface.
Point Reyes Networks/CEMIP Networks 12/00 to 5/01
Principal Hardware Engineer
• For Point Reyes - Lead the development of a scheduler algorithm coded in Verilog
and targeted for Xilinx 600E.
• For CEMIP, successor to Point Reyes, specified system architecture and
components. Designed state machine in Verilog to configurr TMUX device.
Cyras Systems (Ciena) 12/99 to 12/00
Lead Design Engineer
• Lead the development of a four-port gigabit Ethernet to OC48 SONET frame board.
Used MMC Network Processors and Lara Networks CAM for 802.1D/p/Q processing.
Used MMC switch and Lucent TDAT SONET interface.
• Lead the development of an eight-port 10/100 Ethernet to OC48 SONET frame board
using ATM switch and AMCC Congo OC-12 SONET interface.
Cosine Communications 10/98 to 11/99
Contract Design Engineer
Designed serial protocol interface in VHDL for Orca FPGA.
• Managed group desiging ATM cell transfer FPGA with UTOPIA Master and Slave,
and PCI cores.
• Designed and managed a team that produced a POS PCI packet transfers FPGA
with DMA. Simulated FPGAs using Synopsys PCI testbench.
Lasertronics 07/98 to 08/98
• Designed DSP unit in VHDL using MTI, Synplicity for Altera EPLD9000 device
KLA-Tencor 09/97 to 05/98
• Designed 40K gate Fibre Channel-PCI interface chip in VHDL on an Altera
FLEX10K50 using PCI core.
• Developed models and test bench. Used Synplicity for synthesis and MTI for
simulation
Medianix 07/97 to 09/97
• W rote assembly language programs for DSP.
• Ran ASIC verification tests in test bench using Verilog. Verified results using
CWAVES.
Cypress Semiconductor 01/97 to 04/97
• Designed test suite
• Managed engineers, ran tests to verify Verilog OHCI USB. Host design using PCI
Master/Target and USB Hub/Function models
Netro Corp. 09/96 to 01/97
• Designed test bench for FPGA/ASIC verification in VHDL.
• Designed part of data processing FPGA including Reed-Solomon decoder in VHDL
and synthesized with Synopsys to Altera FLEX10K100 FPGA for ATM system.
WSI 07/96 to 08/96
• W rote data sheet and programming information for new MCU support device family.
Virtual Chips 10/95 to 06/96
• Designed and simulated VHDL and Verilog, 32 and 64 bit, PCI bus cores
Radio LAN 03/95 to 07/95
• Designed two-channel, full-duplex Ethernet controller on Quick FPGA
Escalade 11/94 to 05/95
• Designed VHDL DRAM controller and synthesized on a Xilinx XC4000
Symbol Technologies 09/94 to 02/95
• Designed remote LAN card, featuring PCMCIA interface ASIC, 80188 processor,
EPM5128 CPLD and FLASH memory.
Adaptive Logic 03/93 to 08/94
Director of Marketing
• Managed sales representatives and applications engineers, developed data sheets
and applications notes for a semiconductor company.
David Systems 02/93 to 05/93
Consultant
• Designed XC4010 Xilinx FPGAs for a dual-port Ethernet hub transceiver and buffer
memory manager system using Viewlogic and synthesis.
Actel 03/92 to 02/93
Principal Engineer
• Designed macros to showcase capabilities of new products.
• Specified Architecture and Technology for future families of devices.
• Authored papers articles and application notes explaining the benefits of company
products.
Staff Engineer 08/90 to 03/92
• Designed large macros, including fast adders, virtual FIFOs, and address filters for
the library and product demonstrations.
• Performed competitive analysis on Exemplar, Xilinx XC4000, Altera and Quicklogic
tools.
• Designed using Synopsys VHDL for logic synthesis.
• W rote applications guidebook, articles, papers, and application notes.
Senior Applications Engineer 10/88 to 08/90
• Designed, simulated and documented soft macros ranging from TTL functional
equivalents to multipliers, DMA controllers, and DRAM controllers.
• W rote device data book and system user guide. Authored papers, and application
notes.
Design Consultant 05/87 to 10/88
• Designed and simulated 68020-based graphics system.
Designed and simulated ASICs using the LSI Logic LDS system.
•
Britton-Lee Inc. 01/85 to 05/87
Staff Engineer
• Designed and debugged a 68020-based I/O computer with two SCSI channels
controlled by 8032 microcontrollers.
• Designed 32-bit RISC processor with discrete logic.
• Designed 16 MByte DRAM PCB.
Rolm 07/82 to 11/84
Member of the Technical Staff
• Debugged 2903-based bit-slice board.
• Designed I/O controller board.
EDUCATION: San Jose State University, San Jose, CA 1990
• M.B.A.
California Polytechnic University 1982
• Bachelor of Science in Electrical Engineering
PATENTS
Enhanced Scanning Control of Charged Particle Beam System
•
Application 10/931,321
PUBLICATIONS:
Co-authored a textbook on Architecture and Applications of FPGA’s.
•
Published more than 30 magazine articles and technical papers.
•
REFERENCES:
Available upon request
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