Engineer Design

RESUME Dr. Gary Russell Burke

Nov ****

Address: **** ******* ****** **., ********, CA 93021

Tel: 805-***-****

Status: US citizen

Email: ************@****.***

Web: garyrburke.com

Summary: 38 years of experience with digital design, teaching, research

and management. Familiar with HDL, software, design tools, embedded

processors. Expert in Verilog, reliable FPGA/ASIC design and verification.

Principle Engineer

1991 - 12/3/2011

California Institute of Technology - Jet Propulsion Laboratory

During my 20years at JPL, I have lead many ASIC and FPGA projects for

spacecraft and ground systems, wrote the guidelines and process for FPGA

and ASIC design, created and taught the JPL Verilog ASIC/FPGA design class,

completed many research projects, managed a design group and advised and

helped many ASIC and FPGA designers.

Projects

I was the lead ASIC engineer on a set of 3 GaAs digital ASICs, which were

the main dsp element for a digital receiver. This receiver is used at all

deep space ground stations, and all signals from deep space probes are

received by this receiver.

I was the lead ASIC engineer on a Viterbi decoder. This used 64 identical

CMOS ASICs. These were designed using silicon compiler technology. The

'MCD' decoder is in use at deep space ground stations and is used to decode

signals from Pathfinder (a Mars rover) and Cassini ( a deep space probe

orbiting Saturn)

I was the lead ASIC engineer on a flight transponder SoC ASIC. This part

included an embedded processor, pci interface, hardware decoder and a

great deal of DSP logic.

I was the lead engineer on the CIA SoC ASIC. This flight part used a rad-

hard process. It included a processor, analog logic, interface logic

memory and random logic.

I was the lead design engineer on the PLGT FPGA. This flight FPGA was

designed to be used in MSL, Mars Smart Lander which will be launched in

November. This part was built on a rad-hard FPGA and needed to be very

reliable, as it controls vital parts of the spacecraft such as the

thrusters, the pyros, the relays and power switches.

Management

I managed the avionics group for 5 years. The group had up to 17 engineers

working on a variety of space electronic projects and research projects.

These projects included MER (a successful Mars Rover ), Space shuttle

experiments, LIDAR for precision landing, SIM for precision laser guided

tandem flying satellites. I hired and Mentored many good Engineers

including new graduates.

Research

I invented and developed a fVAX, and device to assist in debugging FPGAs.

The device makes internal nodes visible while the device in normal use. In

that way anomalies can be easly discovered and fixed. Currently it is being

used on the SMAP (earth orbiting moisture detection) development. fVAX uses

a Virtex 5, with an embedded processor and custom logic.

I have also worked on several extreme environment project, exposing FPGAs

to very high and very low temperatures. These involved FPGA test designs.

Recently I completed a project testing a flash FPGA down to -150 degrees C.

I also discovered several techniques for reliable FPGA design, such as H2

and H3 encoded state machines, and modulo checked counters.

I investigated porting my PLGT FPGA design to a Sandia via-programmable

ASIC, and have sample ASIC implementations.

Teaching

To assist Engineers at JPL with FPGA and ASIC design, I teach an annual

class in 3 sessions, beginning intermediate and advanced. This class

teaches the basics of logic design using Verilog, and shows how to create

reliable and robust circuits suitable to space flight. The class has been

very successful, and is usually oversubscribed.

Advisor

I have attended many reviews as an FPGA/ASIC expert and advised many groups

on design practices and techniques. Recently I have advised a research

project on the design of a correlator for VLBI radar use, and a

instrumentation project on an efficient very long header detector. I

VLSI Design Engineer/Manager

1986 - 1991

Start-up companies in San Diego

At CHoPP computer I designed application specific integrated circuits for

use in the CHoPP-1, a new-generation supercomputer. These included register

file and arithmetic chips, using gate array, standard cell, CMOS and

bipolar technologies. The Register File chip is an unusual multi-port

design, due to the architectural constraints of the Computer System. The

arithmetic chips have many architectural innovations to obtain high speed.

The register file chip was manufactured and passed all test vectors

correctly.

At Silicon Connections I defined and designed advanced data path and

arithmetic chips in an advanced BiCMOS technology. I devised a proprietary

chip-testing scheme, and have been granted a patent on this. I set up a

design methodology for standard cell custom parts, including the use of

simulation, design and verification tools. The crossbar chip I designed is

now in volume production.

At Floating Point Systems I designed four Asics for the vector processor

unit of a mini-supercomputer. These parts were delivered and functioned

correctly. I was involved with the chip definition, and was responsible for

the selection of design tools and foundries, as well as the detail design,

layout and simulation. Two parts were implemented in a GaAs gate array

(Vitesse), one part was implemented on an ECL gate array, and the fourth

part was implemented in CMOS, using a silicon compiler (Cascade). I

developed a novel CMOS to ECL I/O circuit for this chip. I also supported

Spice simulation at FPS. I have also evaluated bus structures and cache

architectures for the next generation FPS supercomputer.

Manager of VLSI Architecture Development

1978 - 1986

Fairchild Semiconductor R&D group Palo Alto (Now National Semiconductor)

In the Research and Development group, I developed a family of high

speed ECL arithmetic chips, including a 16-bit multiplier, and a set of ECL

graphic chips. I supervised the development of an ECL standard cell

library, using a double poly high speed technology. I supervised the

development of a cell library using an advanced 1-micron CMOS gate array

(sea-of-gates) technology. I also developed ASIC circuits (high performance

multipliers) using both these technologies. While in the Microprocessor

division, I was a co-designer on the F9445 microprocessor, an early 16-bit

bipolar microprocessor, and led a team designing a 64-bit IEEE floating

point co-processor (F9443). I also worked on board level products and

applications. I was a member of the IEEE committee defining the floating

point standard.

Senior Lecturer in Computing

1973 - 1979

Polytechnic of Central London, London, England.

I taught both undergraduate and postgraduate courses, in most

computing subjects, both hardware and software. I set up and ran a series

of industrial short courses on microprocessors, and designed and

manufactured a single board microcomputer for the course. I supervised many

research projects and spent one year myself as a research fellow,

developing software and hardware for microprocessor control.

In the final year I was on Sabbatical leave, working at Fairchild

Semiconductor.

System Design Engineer

1971 - 1973

Standard Telephones and Cables

I worked on Automatic Data Exchange equipment.

Other Teaching and Consulting

I have taught classes at CalState LA, National University, Santa Clara

University and Foothill Polytechnic.

I have consulted for Cray Computer and UCLA

QUALIFICATIONS

B.Sc. (computer science) 1968

M.Sc. (computer science) 1969

Ph.D. (computer science) 1972

Department of Computer Science, Manchester University, Manchester, England.

Member IEEE, California Teaching Credential (1981).

At Manchester University, I assisted with the design of the MU5 - a heavily

pipelined supercomputer, built with ECL MSI logic. I designed an operand

buffer system, which maintains a steady supply of operands to the

arithmetic unit - using cache and queue techniques.

PATENTS

. Patent awarded on 9445 architecture (overall design) 1983

. Patent awarded on 9443 architecture (on 2-level microprogramming) 1991

. Patent awarded on a non-contact chip test scheme 1990

. IFA Accepted into COSMIC data base 1992

. Patent on integrated delay measurement 2010

PAPERS

. Burke - Practical Aspects of Microprocessors in Control Systems - New

Frontiers in microprocessors Engineers Digest June 1976

. Burke - The Application of microprocessors to Control Systems - and

Survey of microprocessors - Microprocesseurs 1er Seminaire

International November 1976

. Burke - Microprocessors in Control Systems - Microprocessors vol.1

no.1 IPC Technology Press Sept.1976

. Burke, Mor, Suri - Fast processor Does More - Fairchild Journal of

Progress, Fairchild Semiconductor June 1982

. Burke, Fompe, Verhofstat - A High performance Microprocessor for Real

Time Applications - Proc. of the 10th Intl. Conf. on Microelectronics

Nov.1982 (Munich)

. Burke - Control Schemes for Microprocessors 15th Annual Conference on

Microprogramming (MICRO-15 1985) - IEEE Oct. 1987.

. Burke - A Multiport register File Chip - VLSI System Design CMP press

Aug.1987

. Burke - Asics in Space - Asic and EDA March 1993

Burke et al - A GaAs Chip set for a Deep Space Receiver - IEEE

Conference on GaAs, Oct 1993

. Burke - A Case Study of a Viterbi decoder - Design Supercon Jan 1997

. Burke, Whitaker - Jetbvd Asic - NASA Technical Briefs 1997

Mojaradi et al - Application of Commercial Electronics in the Motors

and Actuator systems for Mars Surface Missions -

IEEE Aerospace Conference 2004

. `Burke, Taft - Fault Tolerant State Machines - MAPLD 2004

. Burke Lacayo et al - Operation of FPGAs at Extremely Low Temperatures

- MAPLD 2004

. Stoica et al - Re-configurable Electronics Behavior under Extreme

Thermal Environment - MAPLD 2005

. Chen et al - Impact of Negative Bias Temperature Instability on FPGAs

- MAPLD 2005

. Burke, Oh - FPGA Verification Acceleration - MAPLD 2008

. Burke - Highly Reliable Counters - RESPACE/MAPLD 2011

. Sheldon et al - Operation of FPGAs at Cryogenic Temperatures -

RESPACE/MAPLD 2011

AWARDS

. 'Key technologist' award and 'Recognition of Technical achievement'

Fairchild 1982

. 'Recognition of Technical Achievement' NASA 1994.

. Group Achievement Awards (NASA) 1996-2010

. NASA Technical Achievement Award 2010

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