Engineer Process

CHAN-YUN LEE

*** *** **** **** 408-***-****

Fremont, California 94539 *********@*****.***

SUMMARY:

Results oriented professional with extensive education/industry background, skills, and proven expertise including:

• Ph.D. in Physics

• More than 15 years in semiconductor industry; research, development, manufacturing management, engineering, and international accounts

• Conducted and analyzed research on IC processing techniques

• Designed and supervised the manufacturing process of silicon wafers

• Performed silicon crystal and amorphous thin films growth

• Proven ability to solve software and hardware problems

• Solid leadership skills

• Led scientific group in setting up two new physics laboratories and updated experimental equipment

• Several years of teaching semiconductor physics courses and laboratories

• Authored publications in the field of semiconductor physics

• Achieved several recognition awards

KEY ACCOMPLISHMENTS:

Plasma Etch and Thin Film Technology

• Research and development of new highly integrated electronics & photonics circuits. Pioneering R&D Inventions in new processes and materials.

• Led projects to develop 110, 90, 65, 45, 32nm technology nodes on both logic and memory products.

• Managed key accounts and helped develop 65nm etch technology which has been maturely developed and delivered to product lines. Currently 45nm dielectric etch process is ready and being transferred to mass production for major IC chip manufacturers. The 32/22nm technology with double patterning technique (DPT) is recent focus point.

• Initiated research projects to develop and implement new clean room chip fabrication technologies.

• Assisted the worldwide major IC manufacturers in solving yield-related issues, including high particle counts, polymer peeling, bridging, block etch, plasma damage, endpoint malfunction, etc.

• Initiated and implemented several research projects to develop the most challenging via veil removal and high selectivity low-k processes on a new chemical downstream etch tool. Results have been patented.

• Directed research projects to develop low-k dual damascenes processes in different feature sizes and film stacks. Results were presented in ICMI 2000 and IITC 2001.

• Developed the most advanced oxide etches: multi-level Contact, Via, HAR, SAC, bi-layer and tri-layer dry etch process for worldwide major IC chip manufacturers. The first world SAC process on high-density plasma TCP etcher for 0.7um x 0.38um feature size has been successfully developed with satisfactory production yields. Results were presented to 1997 Semicon Taiwan.

• Took advantage of the plasma sputtering machines and ultrahigh vacuum techniques to grow different types of semiconductor thin films. Studied and applied their physical properties in semiconductor devices design. Performed failure analysis using SEM, and CD SEM.

• Applied FLIR IR technology to study plasma/chamber temperature distribution, heat flux variation, and parts reliability, etc.

• Developed new reducing chemistry process and its capability of cleanliness has been verified. Very high selectivity of resist to amorphous carbon has been achieved and patents filed.

• Technologies :

Design of Experiment (DOE), SPC, Dry and wet etch technology, Endpoint detection (OES), Leak

Detection, Sensor head Development and Manipulation, Signal Processing and Programming, Advanced

Troubleshooting and Problem solving skills, Manufacturer Documentation ECNs, TECNs, SWRs, FMEAs,

Measurement, analysis, Trouble-shooting on Schottky, Planar PN Junction, MOSFET Devices. Thin films

growth (STS PECVD)/plasma-sputtering techniques (MRC PVD), Ultrahigh vacuum technology,

New chamber /process characterization, CD shrink, PR trimming, and Bi-layer and tri-layer dry

development techniques, Double Patterning Technology (DPT), High magnetic-filed Spectrometer

Technology, FLIR IR, Technology, etc.

Applications:

Logic and Memory IC manufacturing: ORNAND, NAND, NOR, Floating gate transistor.

FEOL: Contact, SAC, C1NITE, SiN HM open, Ox Spacer, poly HM etch, a-C HMO.

MOL: Contact

BEOL: 1MOE, 2CE & 2MOE, 3CE&3MOE, Via, TVE, PAD, MOL Contact, SD, DD, SADD, STI-HM,

HARC, Container,

Tools:

Lam 4520XL, 4600, 9400, 9500, 9600, TCP 9100 series and extension, TEL DRM, SCCM SE and SE+,

JI-Ox for Unity and Telius platform, Matrix 200mm Cheetah and 300mm Jaguar systems. JMP,

Statgraphics, STS Multiplex ICP AOE, UNAXIS ICP Reactive Ion Etcher, STS Multiplex CVD, Wet etch

bench, Mass Spectrometer, Spectrophotometer, Chromatography, Varian 3000 Series sputter systems,

Tegal Endeavor tool operation, EVG Bonder, Wet Bench, Semitool SRD01, Branson/IPC asher, MRC PVD

metal sputtering system, ASML Micrascan II+ Stepper, Cybor (RC8) Karlsuss CT62, FLIR IR camera.

Metrology:

Hitachi SEM 4150, 5000, 5200 series, JAL SEM, KLA-Tencor CD-SEM, Opti-Probe 200mm and 300mm,

NanoSpec, Tencor FLX-2320 Thin film stress measurement system, DekTak 300-Si Veeco post-plate

Measurement, High Magnetic field Mass Spectrometer build-up and its applications in isotopes

analysis.

Computer Skills :

Complex computer numerical simulations

Programming Languages: BASIC, FORTRAN, C, SQL, and MatLab.

Hardware: Sun SPARC stations, Convex mini-supercomputer, VAX

Software: MS office, Word, Excel, Power Point, MS Project, MS Visio, JMP, Quartz PCI6

PROFESSIONAL EXPERIENCE:

MATTSON TECHNOLOGY, INC., FREMONT, CA 2011-Present

Staff Process Engineer (9/11- present)

• Critical process development, ownership, and related applications.

• New plasma tool process performance, reliability, and system investigation.

• Key accounts drive force: JDP, demo, escalation, etc.

• Database analysis and set up.

ADVANCED INTEGRATED PHOTONICS, HONOLULU, HI 2010-2011

Senior Scientist (3/10- 8/11)

• In-house process development for new materials and innovative design.

• Principal investigation of projects, programs, demo, escalation, etc.

• Field data collection, analysis, and data library build-up.

• Wafer flow in/out controller.

• New (photonic IC) devices design, manufacturing, and testing.

PRECISION INTEGRATED TECHNOLOGY, INC. Fremont, CA 2009-2010

Chief Executive Officer (4/09- 3/10)

• Project Scheduling/Manufacturing Interface/Outsourcing Specifications

• Ability to create product roadmap and lead the strategy for next generation of technology.

• Publication to community and presentation to executives.

• Advanced technology exploration and new products introduction to customers.

TOKYO ELECTRON AMERICA, Santa Clara, CA 2000 – 2009

Principal Engineer (1/03 – 4/09)

West Coast Process Coordinator (5/01 – 1/03)

Technical Staff (5/00 – 5/01)

• Hosted internal and external (customers) bi-weekly and quarterly technical review meetings.

• Helped new production lines ramp-up from R&D, pilot run, to yield and throughput improvement.

• Solved tool/technology related issues: process performance improvement, technical support on escalation, tool qualifications and sustaining, product lines maintenance. etc.

• Client/Customer Interface and Project Management: managing key accounts for major west coast IC chip manufacturers. This includes material selection, process chemistry, product reliability, throughput and yield evaluation.

• On-site process development and demo lab coordination and supervision.

• ICP programs coordination and monitoring to meet specific customers’ needs.

• Hosted and coordinated daily and weekly technical update meetings.

MATRIX INTEGRATED SYSTEMS, Richmond, CA 1999 – 2000

R & D Technical Staff (3/99 – 4/00)

• New tool specifications comply, installation, qualification, and man power coordination.

• Helped tool owners to set up tool qualification procedure and criteria.

• Trained and mentored machine users in complex cluster tools.

• New tool/chamber characterization, demo, process development, throughput and reliability improvement.

LAM RESEARCH, FREMONT, CA 1994 – 1999

Managing Metal Key Accounts in Taiwan (4/98 – 1/99)

Managing Oxide Key Accounts in South Asia (10/97 – 2/98)

Senior Process Engineer (12/96 – 1/99)

Process Engineer (12/94 – 12/96)

• Managed key oxide and metal accounts: from new tools installation, yield improvement, to product tools maintenance.

• JDP programs coordination and supervision in all aspects.

• Foundry/Customer interface and project management for major IC chip manufacturers in South Asia area.

• On site process characterization and demonstration.

• Managed escalation programs.

EDUCATION AND TRAINING:

Ph.D., Physics, University of Notre Dame, Notre Dame, IN

M.S., Physics, University of Southern California, Los Angeles, CA

B.S., Physics, Soochow University, Taipei, Taiwan

RECOGNITION AND AWARDS:

• 2011 Edition of Who's Who Among Executives and Professionals, New York, NY

• 2011 Selected Personalities in Asia, Rendezvous International, United Kingdom

• 2000 Outstanding Scientists of the 21st Century (International Biographical Center, Cambridge, England, 2004)

• 2000 Outstanding Scientists of the 20th Century (International Biographical Center, Cambridge, England, 2000)

• MARQUIS Who’s Who in the World (16th Edition, 1999, 17 -27th Edition, 2000 - 2010)

• MARQUIS Who’s Who in America (53rd Edition, 1999, 54 - 64th Edition, 2000 - 2010)

• MARQUIS Who’s Who in Science and Engineering (4th Edition, 1998, 5 - 16th Edition, 1999 - 2010)

• The Twenty-Seventh Annual Science and Technology Personnel Research and Study Award

(Chinese National Science Council, Taiwan, 1988)

• The Excellent Researchers Prize (Chinese National Science Council, Taiwan, 1986, 1987, and 1988)

• The Outstanding Academic Publications Prize (Tatung Company, Taipei, Taiwan, 1987 and 1988)

PUBLICATIONS AND PATENTS:

• C. Y. Lee, Physical Review B, 15 August 1987, vol. 36, no. 5, pp.2720-2729

“Relativistic Corrections to the Intrinsic Concentration, the Effective Density of States, and the Conductivity in s-dimensional Semiconductors”

• C. Y. Lee, Physical Review B, 15 March 1987, vol.35, no. 9, pp. 4511-4514

“Relativistic Corrections to the Semiconducting Properties of Selected Materials”

• C. Y. Lee, Physical Review B, 15 August 1986, vol. 34, no. 4, pp.2649-2655

“Relativistic Corrections to the Fermi Energy in s-Dimensional Semiconductors”

• C. Y. Lee, et al. “Measurement of Absolute Photoabsorption Cross Section of Atomic Potassium in the VUV Region”, USC M.S. thesis and abstract presented to APS International Symposium of 1979

• C. Y. Lee, Tatung Journal, Nov. 1984, vol. XIV, pp.221-225

“Construction of a Mass Spectrometer and the Natural Abundance Measurement of Isotopes of Alkali Elements”

• C. Y. Lee, Tatung Journal, Nov. 1985, vol. XV, pp.159-168

“Construction of a Spectrophotometer and the Photoionization Studies of Atomic Helium, Argon, and Potassium”

• C. Y. Lee, et al. “Studies on the Optical and Electrical Properties of Amorphous Silicon Films”, reported to Tatung Semiconductor Division and partially supported by Chinese National Science Council (No. 1983-02-29);

• C. Y. Lee, “The Dynamical Susceptibility of Square Lattice Antiferromagnets”, ND Ph.D. thesis and American Doctoral Dissertations, 1994

• C. Y. Lee, et al. “SAC Etch on Advanced High Density Plasma Etcher”, presented to Technical Symposium of 1997 Semicon Taiwan

• C. Y. Lee, et al. “Method for etching sidewall polymer and other residues from the surface of semiconductor devices”, US Patent No. 6667244, March, 2000

• F. Zhang, et al. Advised and presented to Proceedings of the 2001 IITC, pp.57-59

“Nanoglass E Copper Damascene Processing for Etch, Clean, and CMP”

• Vijay Vaniapura, C. Y. Lee, et al. “Strip Method for Minimal Modification of Conductive Materials”,

US Patent pending, September, 2012

• C.Y. Lee, et al. “Method for Stripping Resist with Minimal Underlayer Carbon Loss in Semiconductor Structure”, US Patent pending, September, 2012

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