Engineer Test

Michael D. Meyer

*** ******** **.

* *** ****, ** *****

408-***-**** **********@*****.***

2

* *******

ATE Test Engineer with experience testing a wide variety of IC's on several

leading Test Systems

. ATE Platforms: Verigy/Agilent/HP 93K P1000, PortScale, and PinScale;

LTX Fusion HF/HFi; LTX Synchromaster; Teradyne Catalyst; Credence/TMT

ASL1000

. IC's tested: ADC's and DAC's for a variety of applications; MUX/DMUX

and SERDES chips for communication systems; BB/MAC SOC ASIC's for UWB

applications; Signal conditioning SOC's for MEMS applications

4 OBJECTIVE

Seeking a Test or Product Engineering position at a solid company with

opportunities for professional growth

PROFESSIONAL EXPERIENCE

SiFlare, Inc. (formerly SliceX) - San Jose, CA May 2010 - February 2011

Fabless Mixed-Signal Semiconductor Startup

Principal Member of Technical Staff - Test Engineering

1

. Developed hardware and software, and supervised and coordinated ATE

subcontractor development of SiFlare's line of high-performance, low-

power ADC's on the Verigy P1000 ATE platform

. Supervised and coordinated preliminary qualification effort of SiFlare

product line

. Coordinated shipment and packaging of wafers and devices

Pulse~LINK - Carlsbad, CA January 2006 - January 2009

Fabless UWB Startup

Test Engineer/Senior Test Engineer

2

. Developed and released hardware and software for ATE (93K P1000 &

PinScale) to test Pulse~LINK products - primarily digital base-

band/MAC ASICs for UWB applications

. Assisted in other areas as needed including review of datasheets,

package substrate layouts, device bonding diagrams, bench board

schematics and layouts, and application board schematics and layouts

Vitesse Semiconductor - Camarillo, CA August 2004 - October 2005

Communications Semiconductor Company

Test Engineer

3

. Developed and released hardware and software for ATE (LTX Fusion) to

test Vitesse products - primarily 10Gbps MUX/DMUX & SERDES products

. Developed and adapted routines and test methods in the Cadence tester

language to test Vitesse products, including controlling HP & Anritsu

BERTs through the GPIB interface

Maxim Integrated Products - Sunnyvale, CA June 1992 - March 2001

Semiconductor Company

Test Development Engineer

4

. Developed and released both hardware and software for automatic test

systems (primarily LTX Synchro) to test Maxim products, including

ADCs/DACs, signal conditioners for MEMS applications, and other data

acquisition products

EDUCATION and TRAINING

BSEE - Santa Clara University - Santa Clara, CA June 1992

Emphasis Area: Circuits, Systems, and Signal Processing

. Member of Alpha Sigma Nu, the Jesuit honor society

Continuing Education & Training

. Completed Verigy (HP/Agilent) 93K Basic, Advanced, Mixed-Signal, and

PortScale RF training classes

. Completed LTX Fusion training class

. Completed LTX Synchro-Linear training class

. Completed TMT ASL-1000 training class

. Completed Teradyne Catalyst training class

. Completed Statistical Process Control training

1

2 Computer Experience

. Systems: HP/Apollo workstation, Sun workstation, Windows PC, LINUX PC,

VAX, AT&T DSP-32, DEC PDP-11

. Programming: Cadence tester language, C/C++, BASIC, Pascal, FORTRAN,

8088 Assembler

. Design Tools: Test Insight Wave Wizard vector conversion tools,

SimVision

Other Activities and Organizations

. Judge - Santa Clara University Senior Design Conference

. Volunteer - First LEGO Robotics League

. Member of The Order of Engineers

. Member of Mensa

US Citizen

References Available Upon Request

Contact this candidate