Michael Surgeon

* ****** **, *****, ** *****

abg4nk@r.postjobfree.com

217-***-****

Professional Summary

Senior Electrical Engineer skilled in digital logic design and embedded

software and familiar with all aspects of product development seeking an

electrical engineering position. Experienced in implementing FPGA and

microprocessor-based systems. Willing to take on challenges in other areas

of engineering.

Skills

Digital logic design with VHDL and verilog.

ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable

Gate Array) development.

Proficient with Xilinx and Altera FPGA devices and development tools.

Good working knowledge of SPI, I2C, I2S and TDM component interfaces and

various memory interfaces.

Familiar with SMPTE (Society of Motion Picture & Television Engineers)

standards for video, audio and ancillary data processing and transport.

Revision control using subversion and git.

Familiar with JTAG (Joint Test Action Group, IEEE standard 1149.1) boundary

scan implementation and test development and Asset Scanworks boundary

scan test software.

Competent at designing hardware which complies with industry standards and

customer specifications.

Experience with Mentor Graphics ModelSim and Synopsys VCS simulation tools.

Knowledge of schematic entry tools from Mentor Graphics and other vendors.

Familiar with C, C++ and Python and the Eclipse development environment.

Experience developing diagnostic tests and test plans.

Comfortable with UNIX, Linux and Windows development environments.

Familiar with Oscilloscopes, Logic Analyzers and related test and

measurement equipment.

Work Experience

Senior Electrical Engineer

Cobalt Digital, Inc.

Urbana, IL

October 2006-November 2014

FPGA and software development for television audio, video and ancillary

data processing equipment that conforms to industry standards.

Completed Xilinx and Altera FPGA designs for several generations of

processing cards and a control panel and the associated design

documentation.

Implemented Microblaze embedded soft processor and associated peripherals

and defined the interface between the processor and processing modules.

Configured multi port memory controller IP to provide DDR memory access for

the processor and the audio and video processing modules.

Developed display driver module to drive the displays of a control panel.

Designed modules to interface the processor to the rotary encoders and

buttons of the control panel user interface.

Created modules to interface to external audio components via I2S and TDM

interfaces.

Developed frame sync (genlock) IP to lock outgoing video to a reference

source using a video frame buffer implemented in DDR memory.

Designed audio, video and ancillary data processing modules based on SMPTE

standards which also incorporated customer requested features.

Developed C++ software modules for control of the FPGA processing modules.

Design updates tracked via subversion and git revision control systems.

Actively assisted with system hardware/software integration and the

transition to production.

Supported the processing cards through their functional lifetimes.

Lead Electronics Engineer

FlightSafety International, Visual Simulation Systems

Saint Louis, MO

February 1993-October 2006

ASIC and FPGA designer for flight simulator image generators and

projectors.

Implemented image rendering algorithms in digital hardware for multiple

generations of flight simulator image generators.

Projector geometry correction performed by digital logic driving digital to

analog converters.

Performed schematic entry, schematic symbol and simulation model creation

and coding and verification of FPGAs used for interface and functional

logic.

Assisted with development of a Video Post Processor PCIe card used with off

the shelf PC hardware.

Provided prototype board testing and debug and developed JTAG boundary scan

tests.

Developed ASIC design methodology for Synopsys synthesis, simulation and

test development tools and participated in evaluation of potential ASIC

vendors. Designed the boundary scan architecture embedded within the ASICs.

Completed logic design, pre-layout simulation, synthesis, scan insertion,

test vector generation, device pinout and post-layout simulation of several

ASIC designs and coordinated with the ASIC vendor during the layout

process.

Performed system simulation and design documentation.

Developed C language programs for simulation data manipulation and results

verification and diagnostic tests to aid board-level troubleshooting.

Created board and cable drawings in Autocad.

Actively assisted with system hardware/software integration and the

transition to production.

Senior Electronics Engineer

McDonnell Douglas

Saint Louis, MO

September 1986-February 1993

Began development of the VITAL 8 Image Generator (design in progress during

divestiture to FlightSafety). Began ASIC and programmable logic device

development, schematic entry and schematic symbol creation, system

simulation and design documentation.

Developed hardware for the ARIGS Artificial Radar Image Generation System

used in the F-14D and

A-6E/SWIP simulators. This pipelined architecture was built with discrete

logic components, programmable logic devices and an embedded processor.

Performed schematic entry, assembly language coding of the embedded

processor, prototype testing and debug, design documentation and assistance

with the transition to production.

Provided technical support for the MIL-STD-1750A microprocessor program.

Education

Bachelor of Science, Electrical Engineering

Southern Illinois University

Edwardsville, IL

June 1986

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