RITWIK CHAUHAN
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**** **** ****, #****, ***** Texas 75025, USA (cell) 1-408- 600-9764,
email: abg39o@r.postjobfree.com
Objective
To excel in the role of a SoC design verification engineer and help deliver
high quality SoC designs
Career Summary
. 10 plus years of experience in ASIC design verification working on a
variety of technologies
. Multiple extremely successful ASIC tape-out cycles with extensive
experience working on huge, extremely complex, cutting edge ASIC
architectures and applications
. Expertise in ASIC design verification with extensive experience
implementing & utilizing constrained random verification, transaction
level modeling, functional coverage, assertions, design verification
architecture, and verification methodologies
. Experience working with cross functional teams and internal & external
customers
Professional Skills
. Hardware Description Languages-Verilog HDL, VHDL, SystemVerilog
. Hardware Verification Languages-SystemVerilog-OVM, Vera-RVM, Vera-NTB,
Specman e language
. EDA tools - HDL Simulators(VCS, Modeltech, NCSim), HDL debuggers(Novas
Verdi), Formal Verification(Jasper)
. Database management - ClearCase, CVS, DesignSync
. Programming languages - C, x86 assembly, Perl
Professional Experience
Texas Instruments., USA
February 2011 - Present
Soc Design Verification Engineer
Mobile Base Station SoC
. Next generation of Base station Mobile SoC design for use with
LTE/UMTS standards for NSN(Nokia Siemens Network)
. SoC has PHY layer air interface and network coprocessor functionality
for traffic management
. Technical lead- leading a team of 3 local DV engineers and several
off site team members in geographically diverse locations - DV
strategy, technical leadership, schedule planning, task assignment et
al
. Working on IP packet based network co-processor top level and IP
reassembly verification
. Design verification architecture development, methodology using
SystemVerilog
Qualcomm Inc., USA
May 2006 - January 2011(Contractor till July 2008)
SoC Design Verification Engineer
Next generation Multi-mode Wireless Modem (LTE, WCDMA, CDMA 1x,GSM)
. Next generation multi-mode air interface Modem for LTE, UMTS, CDMA,
GSM standards for network operators world wide
. Technical lead - successfully lead a team size of 4
. Design & verification of Rx demodulator-backend HW chain for LTE,
UMTS, & CDMA technologies using SystemVerilog OVM
. From scratch architecture of SystemVerilog OVM testbench environment &
coming up with verification strategy
. Developed complex agents, sequences, scoreboards, functional coverage
collectors, monitors & other DV components
Multi-mode Wireless Modem (LTE,WCDMA,CDMA 1x,GSM)
. Next generation multi-mode air interface Modem for LTE, UMTS, CDMA,
GSM standards for Verizon wireless
. Design verification of crucial Modem programming infrastructure block
and LTE search blocks using Vera HVL - RVM based verification
methodology
. Co-verified RISC processor & co-processors embedded within the design
using ISS & directed scenarios
. Technical lead- verification planning, strategy, technical mentoring
& providing technical leadership for a team size of 2
. Creation of sophisticated, constrained-randomized, fully automated
verification environments from scratch for achieving very high RTL
quality - zero bugs found in post silicon bring up
. RTL debug, coverage, regressions, testplans, reviews
. Silicon successfully cleared IOT and released by Verizon wireless as a
USB data card device for LTE access in US market
Ultra Mobile Broadband Modem(4G UMB)
. Verification of RxFFT, Tx-chain and Modem bus blocks using Vera HVL
RVM methodology
. Creation of sophisticated, constrained-randomized, fully automated
verification environments for achieving very high RTL quality - zero
bugs found
. RTL debug, coverage, regressions
Universal Broadcast Modem (TV on Mobile phone applications)
. Vera RVM based Verification of a Silicon for use in Modem OFDM
Receiver solutions for supporting TV on Mobile phone applications for
all video standards - ISDB, DVB and FLO
. Verified FFT Engine VHDL module design, developed Vera RVM based LLR
interface driver to the FFT design, fixed existing Vera test bench
issues and plugged in missing features
. No issues found in silicon- ASIC being used by Verizon & other
operators for MediaFlo mobile TV
Centillium Communications, Bangalore, India
June 2004-May 2006
Senior ASIC Engineer
Ethernet Over Optical Network Unit(EPON) ASIC
. ASIC used as an Optical Network Unit in an EPON(Ethernet Over Passive
Optical Network, IEEE 802.3 ah)) for Broadband Internet Access
Applications
. Functional Verification of Bridge Module confirming to IEEE 802.1Q
standard. Developed a robust block level verification environment with
modules like Packet Generator, BFM, Predictor, Monitor, and Checker
using Vera HVL
. Board level Silicon Validation using SmartBits(Spirent)
. Interacting with Customers from Japan for resolving technical issues
. Maintaining and running regressions for full-chip Verification
. Instrumental in conversion of existing Vera based Verification
environment to VCS-NTB
. ASIC being used in broadband networks by NTT Japan
VDSL2(G993.2) ASIC
. Instrumental in developing automated verification environment for full
chip verification in Vera-NTB
. Independently developed complete verification environment for Ethernet
interfaces MII, GMII, SMII, SSSMII, RMII and ATM Utopia level 2
interfaces. The verification environment included the stimulus data
structure, Generator, BFM, Monitors, Scoreboard
eInfochips Private Limited, Ahmedabad, India January
2001-May 2004
ASIC Engineer
Ethernet/PPP/HDLC Over SONET Framer Mapper ASIC, Transwitch Corporation
. Functional Verification of Mapper-Demapper RTL Modules
. Developed verification environment in Specman e HVL, identifying test
scenarios from standards & functional specs, running regressions,
scripting
. Identified & debugged chip level validation problems after recreating
them at RTL level
SONET Framer Mapper ASIC -Intel, Raleigh, USA
. Functional Verification of Buffer Structure Memory Controller (BSMC)
serving 19 requestors in both ingress & egress directions. The BSMC
governed access to a QDR SRAM by means of a sophisticated arbitration
mechanism
. Developed complete verification environment for BSMC RTL consisting of
transaction data structure, generator, driver, predictor, monitor,
checkers in Specman e language. Modeled a QDR SRAM in e language
having the same latency as third party memory models
Gigabit Ethernet eVC(Specman e language verification component), Verisity
Inc.
. Development of verification modules like drivers, monitors, scoreboard
for XGMII & XAUI interfaces in Specman e language
Modem SoC, Agere Inc, Pennsylvania, USA
. Development of an automated verification environment for JTAG RTL
confirming to IEEE 1149.1 using legacy C & VHDL code
. Environment was developed in Verilog HDL & Perl with a facility to
drive JTAG instructions which were read from a test case & comparing
the RTL outputs with reference data
Echo Canceller (ITU G-168) Core, Indian Space Research Organization(ISRO)
. Development of an automated verification environment for PCM
Coder/Decoder using Verilog & Perl for a FPGA implementation of Echo
Canceller IP Core
. Developed Reference model in Matlab for Tone detector fulfilling G-164
criterion
DSP FIR Filter, Indian Space Research Organization (ISRO)
. FPGA based RTL Core for use in digital filter on-board Satellites
deployed by Indian Space Research Organization
. Co-designed functional/design specs, RTL coding of FIR filter using a
look-up table architecture
. Co-designed device validation environment based on 8751 controller
Education
. Bachelors of Engineering in Electronics from South Gujarat University,
India, 2000
. VLSI Engineering Certificate Course, UC Santa Cruz, CA, USA, 2010