Engineer Design

GREGORY M. LAWRENCE

P. O. Box ***

Residence:480-***-****

Chandler, AZ 85244

Cell: 610-***-****

E-mail: ************@***.***

OBJECTIVE

Seeking employment with an aggressive organization that promotes

creativity, quality, and innovative solutions in their products to further

the success and the profitability of the company.

SUMMARY

A Product Development / Technical Support / Testing Engineer with in-depth

semiconductor physics knowledge and experience in Embedded Microcontroller

Architectures, Flash Memories, VLSI CMOS mixed-signal devices, wafer /

package assembly and testing, data analysis, Design-of-Experiments (DOEs),

characterization, validation, qualification, and high volume manufacturing

principles. Demonstrated leadership ability as Product Team Leader

coordinating the efforts of Product Development Teams consisting of

(Design, Wafer Fab, Yield Enhancement, Testing, FA, and Application

Engineering) for developing new microcontroller products. Managed multiple

complex domestic and international product engineering projects involving

wafer fabrication and packaging, simultaneously to transfer new device

designs into production. Able to employ analytical, statistical, root cause

/ corrective action methods for device yield improvement, failure mode

analysis, design performance enhancement, and customer satisfaction. A self-

motivated team player with the ability to perform independently or in team

environment. Possess excellent written / verbal communication and

organizational attributes.

WORK EXPERIENCE

MICROCHIP TECHNOLOGY - Advanced Microcontroller Architecture Division

(MCU 16-bit Group) Chandler, AZ

2006 -

Principal Product Development Engineer

Responsibilities included providing team leadership for assigned MCU 16-

bit products from their design stages through the product life cycle. Task

entailed developing and maintaining project and manufacturing schedules,

generating any needed wafer fab bill-of-materials (BOM) and change

notifications, tracking prototype / production wafer lots through

fabrication, assembly, analyzing testing data, and generating engineering

samples for validation, customer prototypes, and characterization

analysis. Also, orchestrated all qualification activities for the new

products or the re-designed products. Identified or developed procedures /

methods to increase productivity / yield during and after the Release-to-

Production Phase of the new product.

. Serving as Product Lead coordinating activities and maintaining

schedules for design, wafer fabrication, ATE testing, yield

enhancement, failure analysis, and qualification efforts to release to

production Microchip's 1st 280K (0.25 um hybrid) Product. This is an

important strategic project for Microchip because Microchip owns the

280K Process Technology.

. Released Microchips 1st MCU-16 bit 5V/3V Product Family to production

[(fabricated in Microchips 200K Technology (0.35um hybrid)]

GREGORY M. LAWRENCE 610-***-**** Page 2

. Worked with wafer fab facilities TSMC [Taiwan Fab (3) and USA Fab

(11)], Microchip Gresham and Tempe to developed and maintain

manufacturing schedules for assigned new MCU 16-bit products.

. Developed and implemented Comprehensive Characterization Programs for

assigned new products that included normal and process skewed samples.

. Provided sustaining support for assigned product families e.g., high

volume yield manage-ment, failure test / data and yield analysis,

tracked wafer sort and final test yields, identified / resolved major

failures modes, and presenting assigned yield status at MCU16 Monthly

Yield Quality Meetings.

. Held meetings with Corporate Quality and Applications Groups, Test

Engineers, Product / Test Managers to resolve customers issues /

complaints.

. Supported various Microchip Design / Validation Groups by managing all

their Test Chip Module assembly logistics ranging from layout design

changes to complex assembly operations.

. Developed test programs and vector files for the Lynium ATS4000 Analog-

to-Digital (ADC) Tester and characterized the ADC peripherals on

assigned new products.

INTEL CORPORATION - Product Development Quality / Reliability Group

Folsom, CA

2005 - 2006

Product Development Quality and Reliability Engineer

Utilized failure analysis test system (FAT6) to perform indepth physics

based failure analysis on Intel's next generation 90nm and 65nm Flash

Memory designs.

. Worked on cross-functional design / analysis teams to debug flash

design and processing issues that drive package / wafer level

corrective actions plans that includ re-design or test development

modifications.

. Utilize 65nm test chip failure mechanisms to characterize and predict

the overall quality and reliability of the 65nm process.

. A member of a global failure analysis team (members are from countries

China, Hong Kong, India, Philippines, and USA).

SAPPHIRE SOUND STUDIOS, Allentown, PA

2001 - 2005

Chief Recording Engineer

Coordinated and supervised all studio recording projects on a daily basis.

. Responsible for design, development, and implementation of all new

recording techniques.

. Maintained all studios computers systems hardware / software

installations and upgrades.

. Provided engineering services for all studio integrated digital and

analog systems.

GREGORY M. LAWRENCE 610-***-**** Page 3

. Purchased and validated new recording systems. Wrote system operating

procedures for all

new equipment. Equipment list includes 24-Track 8-bus recording

console, DAT recorders, ADAT optical recorders/controllers, PC's

modified with specialty Firewire and USB recording capabilities,

compressors, expanders, equalizers, limiters, digital/analog effects

processors, and various microphones.

AGERE SYSTEMS (Formerly Lucent Technologies, AT&T Microelectronics, Western

Electric), Allentown, PA - Computer Products Group

1997 - 2001

Senior Product Engineer

Responsible for all product engineering activities for the Firewire, USB,

and ASIC VLSI CMOS mixed-signal devices from the prototype stage through

the product life cycle. Task entailed generating bill-of-materials (BOM)

and change orders, tracking prototype/production wafer lots/package lots

through fabrication and analyzing lots' specific intrinsic

characterization data,

coordinating wafer/package characterization testing for models and

performing detailed data analysis for prove-in/validation, and

orchestrating logistics to transfer models into production

for mass manufacturing.

. Orchestrated wafer manufacturing activities with wafer fab facilities

at Agere Systems (Bangkok, Singapore, Madrid, Allentown and Orlando).

. Utilized various quick-turnaround packaging facilities to produce all

USB, Firewire, and ASIC VLSI CMOS mixed-signal prototype models.

. Worked closely with testing engineers to define ATE testing limits

based on correlation data

from bench testing or product yield analysis.

. Participated as primary product engineer in design reviews for USB,

Firewire, ASIC VLSI CMOS devices.

. Engaged in the ongoing analysis of wafer/package yield data from US

fab/testing facilities (Allentown, PA and Orlando,FL) and foreign

facilities (Madrid, Singapore, and Bangkok).

. Researched and implemented a 128 pin-TQFP 0.5mm pitch package design

into a 120 pin -TQFP 0.4mm pitch package to meet customer demands

resulting in revenue of $8 million per year.

. Orchestrated containment/corrective action procedures for non-

complying device products at internal and customer warehouses that

saved an estimated $3.9 million.

. Performed indepth failure mode analysis for a USB device that resulted

in an increase in wafer yield from 31% up to 92%, wafer processing

hydrogen anneal temperature change, and a USB bus transceiver re-

design.

AT&T MICROELECTRONICS - Customer Technical Support Center

1996 - 1997

Technical Support Engineer

Performed duties as a liaison between internal VLSI CMOS mixed-signal

design/testing teams and external customers to resolve device quality

issues. External customers were both domestic and

international.

GREGORY M. LAWRENCE 610-***-**** Page 4

. Duties included in-taking RMA's, processing, tracking, investigating

all device quality issues, reporting to customers all findings and

instituting corrective actions.

. Worked with design teams to reduce or eliminate device quality issues

that ultimately resulted in cost saving and customer satisfaction.

AT&T TECHNOLOGY SYSTEMS - Quality / Reliability Group

1986 - 1996

Reliability Planning/Test Engineer

Utilized ATE to perform HTOB, Temperature Cycling, Moisture Resistance

reliability and qualification testing to support all AT&T manufactured

CMOS VLSI memory, ASIC, and DSP devices using AT&T's Qualification

Specifications, MIL-STD 883, and EIA/JEDEC standards.

. Developed a wafer fab reliability monitoring program for wafers

manufactured in AT&T Madrid, AT&T Orlando-1 and Orlando-2, AT&T

Allentown's MOS 5 and MOS 2, TSMC,

and Chartered Semiconductor.

. Provided valuable steady state life testing data for joint Bell Labs'

Early Field Failure Rate (EFFR-QIT) Quality Improvement Team's Step

Stress Acceleration Factor Study on the 0.5um (3V/ 5V) and 0.35um

Standard Evaluation Circuit (SEC).

. Engaged in ongoing reliability testing support and characterization

activities for the various VLSI memory and ASIC devices from different

wafer fabrication and packaging locations.

. Other duties included ATE loadboard designing, ATE system

installations, troubleshooting software/hardware problems, modifying

firmware and software programs, writing shop and maintenance operation

documents, developing testing plans, and maintenance calibration

schedules.

. Developed an Electro-static Discharge (ESD) Training Program that

provided training and ongoing qualification/certification of shop and

management personnel.

EDUCATION

M.S., Electrical Engineering; Clemson University; Clemson, SC

B.S., Electrical Engineering; Savannah State University; Savannah, GA

Microsoft Certified Professional; Information Computer Systems Institute;

Allentown, PA

Microsoft A+ Certified; Information Computer Systems Institute; Allentown,

PA

Multi-Track Recording Diploma; Institute of Audio Research; Manhattan, NY

TECHNICAL ADDENDUM

Test Systems: Lynium (ATS4000) Analog-to-Digital Tester, NexTest (FAT6),

HP83000, Advantest, Micro Control Company (HTOB) Memory Life Test System,

Aehr Burn-in System, LTX (DX90, TS80/TS88) Analog Test System, Blue-M

Moisture Resistance Systems.

OS/Environment: Lynium (ATS4000), Windows 7, Windows 2003 Server, Windows

2000 Advance Server, Windows 2000 Server, Windows 2000, Windows XP, Windows

ME, Windows 98, Windows 95, Windows 3.1, UNIX, C, C++, Macintosh, LTX

Basic, MCC Basic, and Assembly Language.

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