Tianxiang Huang

ab9pzu@r.postjobfree.com ** Rio Robles E, #1211, San Jose, CA, 95134 614-***-****

Objective:

Seeking for a position in IC/hardware design engineering, mainly in the area of analog circuits design, RFICs, RF

system, mixed signal, and electronics.

Qualifications:

• Analog/Digital and RF transceivers design in CMOS technologies, including filter design, matching network,

Opamp, Logic gates, ADC/DAC, LNA, Mixer, VCO, PLL, PA.

• Experience in CAD schematic tools, Cadence (Virtuoso, SpectreRF), ADS, Spice, verification and familiarity

with test equipment, such us spectrum analyzers, network analyzers, oscilloscopes, and signal generators.

• Knowledge of Verilog, VHDL, digital signal processing.

• Experience in PCB layout design, and knowledge of EMI/EMC.

Education:

The Ohio State University, Columbus, OH GPA: 3.61/4

The Master degree, Majored in Electrical and Computer Engineering, May 2013

The Zhejiang University of Technology, Hangzhou, China GPA: 3.1/4

The Bachelor of Science, Majored in Optical Science and Technology, July 2011

Experience:

ElectroScience Lab, Ohio State University, Columbus, OH

Graduate Student Researcher, March 2012 – June 2013

Design experience in transistor level RF front-end circuits and blocks, working on schematic design, and

hands-on experience. Participated in the research of adaptive optical MEMS device and mircofabrication.

Yinxiang Machine Tool CO., LTD, Zhejiang, China

IC Engineer (internship), June 2010 – September 2010

As a team member, worked on microcontroller system to drive thermal printer head IC, which operates

shift-registers, latches and switching transistors to control heat elements. Dealt with ASCII characters

converting into printable form and controlling corresponding heat units according to shifted data. Also

experience of DSP.

Projects:

Ultra-wideband Resistive Feedback CMOS Low Noise Amplifier (Mar - Apr 2013)

• A current reused LNA was designed for wide band (3G~10GHz) receiver, using 90nm processing technology.

• Resistive feedback, matching network and gm-enhanced cascade topologies were applied in LNA design.

• Off chip buffers were implemented in test bench. With power consumption of 15mW, achieved high and flat

gain of 18 dB, NF < 5dB, S11, S22 below -10 dB and IIP3 of -8dBm.

High IIP2 WCDMA Mixer for Direct Conversion Receivers (Mar - Apr, 2013)

• A WCMDA band mixer was designed to achieve high linearity for down conversion purpose.

• A differential double balanced mixer was designed to achieved IF band (5MHz). LO switch pairs and RC

filters are optimized to reduce noise.

• Achieved 50~60 dBm IIP2 and 10 dBm IIP3. With 12 mW power consumption under 1.2V supply voltage,

the conversion gain was around 11 dBm with noise figure of 9 dB. Stability was measured.

Low Phase Noise VCO for PCS Band (Apr - May, 2013)

• A NMOS VCO worked at the GSM upper frequency bands (DCS1800 and PCS1900), 1710~1900 MHz.

• Differential LC VCO was designed and 4bit switched-capacitor networks were implemented for coarse

tuning.

• With 30 MHz/V Kv for each single band, the worst phase noise at 400 kHz was less than -110 dBc/Hz and

less than -150 dBc/Hz at 20 MHz, and power consumption was 10mW including on chip VCO buffer.

Class-A Power Amplifier for Bluetooth System (May, 2013)

• A PA was designed for Bluetooth standard transmitter with power gain of 5 dB with modulation type GFSK.

• Two stages were applied to increase the efficiency and gain. Matching network is design.

• The system had 8% efficiency with phase noise less than -130 dBc/Hz. Achieved 2dBm P1dB with output

power of 0 dBm, and 2nd/3rd harmonic levels of less -20/-30dBm.

SPICE model PLL Design for Mixed Signal System (Mar-May, 2013)

• A low power PLL was designed in Hspice based on 0.18um processing, with carrier frequency of 200 MHz.

• Current mode phase detector, fully balanced charge-pump, loop filter were designed. Single balanced VCO

worked at 1.6 GHz with 40 MHz tuning sensitivity. A 1/8 fractional-N divider was also implemented. Netlist

was coded and circuits debugging was performed.

• Achieved -118 dBc phase noise @ 1MHz, 280nS lock-in-time, and 9.75 mW consumption under 1.8V.

6-bit 1.25 GS/s Flash A/D converter in 90nm CMOS technology (Nov, 2012 – Jan, 2013)

• A 6bit Flash ADC was designed for high speed communication system, and occupied 0.6mm 2 chip area.

• Working at 1.25GS/s sampling rate, S/H stage, differential preamplifiers, SR latch, Comparators, digital

encoder were implemented.

• 132mW consumption under 1V supply voltage, achieved DNL and INL of +0.52/-0.47LSB and +0.7/-

0.49LSB respectively. With Nyquist input, SNDR is achieved as 33.2 dB, and SFDR of 39.8dB. The ENOB

measured has peak value of 5.8 bits.

Rat-Race Hybrid Coupler for RF system ( Oct-Nov, 2012)

• Designed a four-port Rat-Race network with 180 phase shift at center microwave frequency of 2.4 GHz.

• The circuit was simulated and optimized in ADS. And the layout was obtained for tape-out.

• The validity of device was tested by vector network analyzer. Each port of S-parameter was measured.

Adjustable Power Supply Board Design (Feb-Apr, 2012)

• A board level dual polarity power supply was designed based on OrCAD, with LM317 / LM337

implemented.

• Circuit schematic in Pspice model was simulated and verified. PCB was designed and optimized after DRC

performed, including LVS, electrical rules, physical rules, and Layout routing was manually built.

• Circuit board was tested. Output voltage ranges from +/- 5to 12V and 1A max current.

Operational Amplifier Design (Oct-Nov, 2011)

• Designed a differential op amp with 90MHz bandwidth in Cadence Analog Artist.

• Apply folded-cascode topology, achieved voltage gain of 50dB, 45 degree of phase margin, slew rate of

23V/us, linear output swing of 1.5V and 1mW power consumption.

The Supervisory and Control System of GSM Iraser (Jan – Apr. 2011)

• Designed embedded system to make a pre-warning of the safety risk in the security area.

• The system is based on GSM module, SIEMENS TC35i, and STC89C52 micro controller based on C

programming, and module transmits data or information to cell phone by Hayes command set.

High Speed MOSFET Device Optimization (Apr- May, 2012)

• The 2D MOSFET were built and tested in the software of Silvaco.

• Contrasting the different type of MOSFET in long and short channel devices, obtain the current curves.

• The behavior of semiconductor device was performed. Threshold voltage shift and Drain Induced Barrier

Lowering (DIBL) are also simulated depending on different gate length.

Software Skills:

Programming: Matlab, C/C++, Visual Basic, Verilog, Matlab

Electrical Design: Cadence Virtuoso, Spectre RF, Allegro OrCAD, Sonnet, Agilent ADS, Simulink, HSPICE,

SystemVue, Labview

Others: Silvaco, Protel, COMSOL AutoCAD, Solidworks, Zemax

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