Software Computer Science

Curriculum Vitae

Sean Halle

Address Personal Details

Carolina Macgillavrylaan 1976 Nationality: US

1098XE Amsterdam Gender: Male

Tel : +31-616-***-***

EMail : *********@*****.***

Overview/Summary

Sean is a researcher, and former entrepreneur. As an undergraduate and masters student, his research

at UC Berkeley demonstrated the first evidence of secure communication using chaos, spread spectrum

communication using a chaotic carrier signal, and gain from perturbation of chaotic circuits, with a total

of 680+ citations to these papers. He left with his Masters in 1994, to pursue starting a company with

technology developed during a graduate course, eventually founding a fabless chip company around a

massively parallel MIMD-SIMD low-power processor for graphics (ProSide), in 1997. After the company’s

demise, he switched to software and worked his way up the chain, ending at Chief Software Architect at

Nevik in 2000. The dot-com crash precipitated a return to academia to start his PhD in 2003, where

he worked on parallelism, developing a theory of parallel computation, and a performance-portable

software stack. As part of this, in 2008 he was invited by Albert Cohen to work in Paris at INRIA, the

national computer science research institute for France, concentrating on new parallel languages for high

productivity and high performance portability. This led to BLIS and proto-runtime, two technologies

that became the basis of his dissertation, for which he received his PhD in 2011. He subsequently

advanced the proto-runtime work as a post-doc at TU Berlin, and is currently advancing it further as

an ERCIM fellow at CWI in Amsterdam.

Education

May 1992: UC Berkeley, BSEE, Dept. of Electrical Engineering and Computer Science.

May 1994: UC Berkeley, MSEE, Dept. of Electrical Engineering and Computer Science.

Thesis on Experimental Chaos. Published the first papers in the field on "Gain from

Chaos," "Spread Spectrum Communication Using Chaos," and "Secure Communica-

tion Using Chaos." The papers, combined, have garnered in excess of 450 citations.

Advisor: Leon O Chua.

June 2011: UC Santa Cruz, PhD, Dept. of Computer Engineering.

Dissertation on theory of parallel computation and tools for delivering performance-

portable parallel software . Advisors: Albert Cohen (INRIA, Paris), and Jose Renau

(UC Santa Cruz).

Experience

Apr ’13 to Apr ’14: ERCIM Fellow at CWI in Amsterdam.

Implementing the Reo language on top of proto-runtime, and extending proto-runtime

to distributed machines, developing on the Netherlands’ national supercomputer.

Jun ’11 to Jun ’12: Post-doctorate researcher at Technical University Berlin.

Oversaw 6 students who worked on: verifying the Holistic Model of Parallel Com-

putation (proposed in Dissertation), design of a low-power GPU that is free from

programming and application restrictions, improvement of proto-runtime, and imple-

mentation of the HWSim language on top of proto-runtime.

Apr ’08 to Apr ’11: INRIA, Paris and Ecole Normale Supereur: Performed research on Portable High

Performance Parallelism.

In 2008-2009 period demonstrated DKU and BLIS framework in Java and in C, run-

ning on multi-core shared memory machines, a heterogeneous collection of them and

on the Cell processor. In 2010 and 2011 designed WorkTable language for high produc-

tivity parallel coding for Enterprise applications, and HWSim for high-performance

simulation of hardware designs, using parallel host machines. In 2011 delivered Vir-

tualized Master-Slave (VMS), a hardware abstraction to simplify creation and imple-

mentation of domain-specific parallel languages, and the basis of a software stack for

performant-portable parallel software. The work there formed the main results in his

dissertation.

Sept ’03 to Apr ’08: UC Santa Cruz: Performed research on a theory of parallel computation, and

developed a programming system for performance-portable software called CodeTime,

in addition to an analytic performance model for out-of-order pipelines.

Apr ’02 to Sept ’03: Freelance: In anticipation of starting a fabless chip company, architected an ultra

low power multi-threaded high-throughput processor. Developed a detailed analytic

model of the processor. Wrote behavioral code and a test suite to demonstrate its

performance. Pursued series-A funding.

Dec ’00 to Apr ’02: Nevik Networks: As Chief Software Architect, designed and was responsible for the

team implementing a telecom abstraction layer that provides web-based end-customer

provisioning of big-iron class 5 switches as well as soft-switches. Led development,

drove requirements gathering and scoping of the product.

Dec ’99 to Dec ’00: SRI International: A member of SRI’s enterprise software consulting spin-off. De-

signed a high speed trading system for Deutsche Bank’s fixed income securities mar-

ket. Co-architected, for American Century, an integrated financial system. Con-

tributed papers analyzing and detailing electronic exchanges. Technical lead on im-

plementation of a financial planning services exchange.

Apr ’99 to Dec ’99: Cisco Systems, contract: Member of web based ordering tool team ($15 Billion in

orders annually via this tool). Added functionality via modifying front-end servlet

code, back-end business logic, and Oracle database tables.

Apr ’98 to Mar ’99: Sun Microsystems, JavaSoft division, contract: Participated in debug of the AWT

portion of the Java language for the 1.2 release. Contributed to specification of the

automated GUI testing API that later appeared in release 1.5. Developed automated

testing tools.

Mar ’96 to Dec ’97: ProSide Inc. Acquired funding for a novel architecture fusing SIMD and SPMD

of his design. Targeted at 3D graphics, was also a general "loop accelerator" that

appeared as smart-memory. Developed base programming language and tools.

Jan ’95 to Jan ’96: Digital Equipment Corporation: Held position created for him by Dan Dobberpuhl

to evaluate advanced technologies for use in Alpha processors. Evaluated adiabatic

logic, Time-Stationary Computation, and other low power, high speed technologies.

Invented five new logic families and a novel division technique based on deduction.

Designed high speed pseudo-self-timed array multiplier for low cost Alpha core and

StrongArm VLIW co-processor using a combination of static, domino, and differential

cascode (DCVSL) logic.

Personal References

These persons are familiar with my professional qualifications and my character:

Prof. Albert Cohen

Thesis supervisor Phone: +33-1-44-32-21-67

Department d’Informatiqe Email ******.*****@*****.**

Ecole Normale Superieure

45 rue d’Ulm

75005 Paris

France

Prof. Jose Renau

Thesis supervisor Phone: +1-831-***-****

1156 High Street MS: SOE2 Email *****@***.****.***

Santa Cruz, CA 95064

USA

Prof. Farhad Arbab

Principle Investigator Phone: +31-30-314-*****

CWI Email ******.*****@***.**

Science Park 123

1098XG Amsterdam

Netherlands

[12, 14, 16, 10, 15, 17, 11, 4, 3, 9, 5, 7, 13, 8, ?, 6, 1, 18, 2]

References

[1] K.S. Halle, Leon O. Chua, V.S. Anishchenko, and M.A. Safonova. Signal amplification via chaos:

Experimental evidence. Int. J. of Bifurcation and Chaos, pages 290–308, 1993.

[2] K.S. Halle, C.W. Wu, M. Itoh, and L. O. Chua. Spread spectrum communication through modulation

of chaos. Int. J. of Bifurcation and Chaos, pages 469–477, 1993. cited by 232.

[3] Sean Halle. The case for an integrated software platform for HEC illustrated using the codetime

platform, 2005. http://www.soe.ucsc.edu/share/technical-reports/2005/ucsc-crl-05-05.pdf.

[4] Sean Halle. Bactil: Base codetime language, 2006. http://www.soe.ucsc.edu/share/technical-

reports/2006/ucsc-crl-06-08.pdf.

[5] Sean Halle. The elements of the codetime software platform, 2006.

http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-09.pdf.

[6] Sean Halle. A mental framework for use in creating hardware independent parallel languages, 2006.

http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-12.pdf.

[7] Sean Halle. A scalable and efficient peer-to-peer run-time system for a hardware independent

software platform, 2006. http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-10.pdf.

[8] Sean Halle. An extensible parallel language, 2009. http://www.soe.ucsc.edu/share/technical-

reports/2009/ucsc-soe-09-16.pdf.

[9] Sean Halle. A hardware-independent parallel operating system abstraction layer for parallelism,

2009. http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-15.pdf.

[10] Sean Halle. PStack home page – a software stack for performantly portable parallelism, 2012.

http://pstack.sourceforge.net.

[11] Sean Halle. The worktable language reference manual, 2012.

http://musictwodotoh.com/worktable/content/refman.pdf.

[12] Sean Halle and Albert Cohen. BLIS website, November 2008. http://blisplatform.sourceforge.net.

[13] Sean Halle and Albert Cohen. Dku pattern for performance portable parallel software, 2009.

http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf.

[14] Sean Halle and Albert Cohen. Leveraging semantics attached to function calls to isolate applications

from hardware. In HOTPAR ’10: USENIX Workshop on Hot Topics in Parallelism, June 2010.

[15] Sean Halle and Albert Cohen. A mutable hardware abstraction to replace threads. 24th International

Workshop on Languages and Compilers for Parallel Languages (LCPC11), 2011.

[16] Sean Halle and Albert Cohen. Support of collective effort towards performance portability. In

HOTPAR ’11: USENIX Workshop on Hot Topics in Parallelism, May 2011.

[17] Sean Halle, Merten Sach, Ben Juurlink, and Albert Cohen. VMS home page, 2010.

http://virtualizedmasterslave.org.

[18] V. Kocarev, K.S. Halle, K. Eckert, L. O. Chua, and V. Parlitz. Experimental demonstration of secure

communications via chaotic synchronization. Int. J. of Bifurcation and Chaos, pages 709–713, 1992.

cited by 457.

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