Assistant System

**** ********** ***, ***. ***

Cell phone: 513-***-****

Dayton OH, 45420

******@*******.***

Chong Chen

Objective Seeking a full-time research or development position related to high performance

computing, computer programming or computer system

Education University of Dayton Dayton, OH Graduation: May 2014

Doctor of Philosophy, Electrical and Computer Engineering.

Chinese Academy of Science Beijing, China Graduation: May 2008

Master of Science, Space Science.

Xi’an University of Technology Xi’an, China Graduation: May 2005

Bachelor of Engineering, Electrical Engineering.

Research

High performance computing Cluster computing

Interests

Multi-core/Many-core programming Very large linear system solver

Acceleration of Pattern Recognition

and Image Processing algorithms

Skills

C/C++ programming Parallel programming using MPI

GPGPU/Xeon Phi programming Neural network algorithms

Solid background in mathematical

Experience University of Dayton, Dayton, OH Sep. 2009-present

Research Assistant

Very large sparse linear system solver:

Implemented preconditioned iterative in CPU/GPGPU hybrid cluster with

distributed memory system.

Applied High performance sparse matrix vector multiplication kernel function in

GPGPU combined with multi-thread based Factorized Sparse Approximate

Inverse Preconditioner generating function in multi-core CPU.

Conducted High efficiency graph based partitioning method for distributed

computing in many computer nodes.

Designed Communication/computation overlapping to reduce communication

costs between computer nodes.

Achieved 2X speed up when compared with NVIDIA CUSPARSE library in single

node.

Achieved 9.2X speed up in 16-nodes system when compared with single node

implementation.

Large scale Neuromorphic simulation in hetegenrous cluster:

Implement a very large spiking neural network simulation in a heterogeneous

cluster contains three different platforms: Multi-core CPU, GPGPU, and CELL/BE.

Multiple optimization method is applied to accelerate the simulation: multi-thread

and SSE for multi-core CPU, memory coalescing and map reduction for GPGPU

platform, unrolling loops and double buffering for CELL/BE

Used unsynchronized MPI for communication between different platforms with

different speed.

High-speed Industry Robot Calibration

Developed a GPGPU based very large RBF neural network to calibrate the

industry Robot. Implement Coleskey Decomposition in GPGPU for the weight

updating of RBF neural network

Improved the precision by 78%, achieved 300X speedup when compared with

Matlab toolbox.

University of Dayton, Dayton, OH Jan. 2012-

present

Teaching Assistant

Instructor of ECE 314L (computer organization lab)

Preparation of the experiment instruction materials. Each semester usually

contains 11 labs.

Around 30-min lecture at each lab. Answer the questions from the students and

help them to finish the projects.

Design the experiments for better understanding the assembly language

programming and embedded C language programming in microchip PIC32

platform.

Changchun Observatory, Chinese Academy of Science,

Sep. 2005 – May. 2008

Changchun, China

Research Assistant

Design the FPGA based control circuit for high frequency and precision satellite

laser ranging (SLR) system.

Design the image processing algorithm for automatic SLR system

Selected Chong Chen, Tarek M Taha: “ A communication reduction approach to

iteratively solve large sparse linear systems on a GPGPU cluster”, Cluster

Publications:

Computing (journal), accepted and published online at

http://link.springer.com/article/10.1007/s10586-013-0279-2

Chong Chen, Tarek M Taha: “Spiking neural network models on high

performance computer cluster”, Proc. SPIE 8134 (September 12, 2011);

doi:10.1117/12.897269

Messay Teme, Chong Chen, Ordonez Raul, Tarek Taha: “GPGPU acceleration

of a novel calibration method for industrial robots”, Proc. IEEE NAECON

2011; doi: 10.1109/NAECON.2011.6183089

Chong Chen, Cunbo Fan, Zhenwei Li, You Zhao: “Development of the circuit

system in high frequency satellite laser ranging equipment based on

FPGA”, Proc. SPIE 7156 (Jan 27, 2009), doi:10.1117/12.806825

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