Power Plant Project

Sankalpa Sen

**** ********** **** # ***, *******, TX 77063

Ph. 713-***-****

email. *******.***@*****.***

Objective:

To obtain a job in a dynamic setting where I can deliver the best of my capacity and at the same time learn

from real-world challenges.

Experience H ighlights:

R ole: Ha rdware Test Engineer

Company: SAIPSIT

May 2013 – Present

Testing of Mobile and Electronic Devices

R ole: I ntern

Company: SAIPSIT

January 2013 – May 2013

Testing of Mobile and Electronic Devices

Role: Student Assistant

Company: UNT Dining Services

August 2011 - January 2013

R ole: T rainee/Assistant Engineer

Company: Automation And Control Systems Pty Ltd

November 2010 – June 2011

I SA-CIAT t raining on PLCs of Allen Bradley, Siemens, Mistubishi, Messung, M M I, SCADA,

D r ives and IEC Standard Programming

Role: T rainee

Company: Durgapur Projects Ltd

June 2009 – August 2009

T rained on Power Plant Instrumentation

Role: Electronics Repair Technician (Part Time)

Company: Asansol Electronics

J uly 2007 – May 2009

Responsible for repair of mobile and audio/video devices.

Educational Qualifications:

M aster of Science (M.S.), Electrical and Electronics Engineering

U niversity of North Texas (2011 – 2013)

Bachelor of Technology (B.Tech.), Electronics and I nst rumentation Engineering

West Bengal University of Technology (2006 – 2010)

Skills and Areas of Expertise:

V HD L; Verilog; Xilinx ISE; FPGA prototyping; Electronic Circuit Design; Ngspice;

L TSpice; Electric VLSI Design; Cadence Vi rtuoso; Pspice; CPU design; Matlab;

S imulink; Labview; R

Automation; PLC; PLC Ladder Logic; PLC Programming; CoDeSys; PLC Allen

B radley; SCADA; Electric D r ives; Servo D rives; H M Is; M M I

Electronic Measurement and I nstrumentation; Wireless Sensor Networks; Process

Control; Power Plant I nst rumentation; Thermal Power Plant; PowerEsim; Power

E lectronics; Digital Signal P rocessing; Assembly Language Programming;

M icrocontrollers; Embedded Systems; PCB Layout

C; C++; M icrosoft Office; BizTalk; SQL Server Management Studio; Visual C#;

V isual Basic; WCF; XML; XSLT; H T M L; BAM; Windows 7; Windows Server

P rojects:

N ANO SCALE CMOS SRAM DESIGN: A Comparative Study of SRAM Designs

(August 2012 – December 2012)

This project presents different designs simulated using various tools, and makes a

comparative study to focus light on the various static memory design research in today's

h ighly mobile world of electronics. Various designs are simulated (bitcells, word and 8k) at

d ifferent technology nodes and then explained in details and then compared. First, in this

p roject a standard six and eight t ransistor SRAM cell is designed using Spice, using 45 and

32 nm technology for a basic standard of comparison, then, further down the way, various

modifications had been done, which include optimizing the t ransistor dimensions, I/o ports,

reducing t ransistor counts and several other techniques to answer the challenges of such

memory design and produce a most optimized result in terms of performance, dealing with

challenges of power dissipation, leakage, noise margins, area, read/wri te stability, access

t ime(speed) and such other att r ibutes which stills remains a challenge.

Designs Simulated: Standard 6T SRAM, 8T SRAM, Single Ended 6t Sram With Isolated

Read-Port, High Density 4-T Sram,7t Sram Cell For Low Power Cache Design,7T dual-Vt

SRAM,A novel five-t ransistor (5T) sram cell for high performance cache, H igh Density and

Low Leakage Current Based 5T SRAM Cell Using 45 nm Technology,10T Non-Pre charge

T wo-Port SRAM

Tools used: Pspice, L tSpice, Ngspice, Cadence Vi r tuoso, HSPICE,PTM

I ntelligent Battery Management Scemes (November 2011)

Various smart battery management techniques are discussed and designed in this project

and verified with DUALFOIL.

4G Wireless Systems (August 2012 – December 2012)

Directed Study

H264 encoder in V HD L (February 2012 – May 2012)

The H.264 hardware encoder is designed on a as a modular system with small, efficient, low

power components doing well defined tasks implemented on Xilinx Vir tex 5 FPGA. The

p rinciple design aim was to make an scalable encoder for megapixel images suitable for use

i n camera heads and low power recorders.The encoder is not designed to be all things to all

people, but rather designed to efficiently implement a non-interlaced Base Profile with no

l imit to the number of streams or video resolution.

32 bit Advanced P rocessor Architecture Design (February 2012 – April 2012)

In this project a basic 32 bit processor is designed using VHDL and then advanced

a rchitectural features are added to this basic processor design. These features include

p ipelining, superscalar execution, branch prediction, and advanced cache features. A fully

f unctional model is then implemented in Xilinx Vi r tex 5 FPGA.

RaPiD CGRA ( March 2012)

Xilinx ISE based Project on coarse grain reconfigurable architechture for achieving more

power efficiency, density and speed while not compromising on f lexibility.

Robotic Vehicle (April 2012)

An autonomous vehicle is designed in this project, which has a control system which can

detect path edges and avoid collisions, along with basic functions of a vehicle, programmed

i n LabView, implemented using Lego NXT M indstorm robot.

H igh Performance CMOS Op-Amp Design (January 2012 – March 2012)

A high performance CMOS op-amp is designed using cadence vir tuoso, focusing on areas

w here increased performance is desired like lower output resistance, larger output-signal

swing, increased slew rate, increased gain bandwidth, lower noise, lower power dissipation.

Single Ended Six T ransistor SRAM with Isolated Read Port (November 2011)

A single ended SRAM 6T bitcell design and i ts word orientation for robust, high density and

low power SRAMs is simulated in this project. The desired features of a memory design for

low power cache is achieved by isolating the read current path. The improved read and

w r ite-ability, reduced active and leakage power dissipation compared to standard 6T and 8T

b itcells.

B inocular Stereo (October 2011)

A Matlab program was developed to partially reconstruct a 3D perception from two stereo

i mages taken with left eye and r ight eye using an un-calibrated camera. The algorithm

d isplays the two images and the user matches corresponding points in both images. From

t he displacement of the selected image points the algorithm estimates a depth surface for

t he scene. The original image is then” draped” over the depth surface to create a depth field

on the image.

Sawtooth Relaying (using MATLAB) (September 2011 – December 2011)

This project focuses on a three-node AWGN relay channel with a memory less relay, in

comparison to the t raditional decode and forward and amplify and forward schemes, which

needs complex relay designs for encoding and decoding processing. Instead a memoryless

relaying scheme is used where the operation of the relay is based on a single variable

deterministic mapping. A modulo function or a t r iangular function is used to implement the

mapping at the relay. These functions are sawtooth in shape so this relaying scheme is

called sawtooth relaying This relaying scheme largely closes the performance gap between

memoryless amplify and forward relaying and conventional relaying schemes with long

memory and high complexity.

Automatic Speaker Recognition System (October 2011 – November 2011)

This project aims to build a simple, yet complete and representative automatic speaker

recognition system. Due to space limitations the system is tested on a small speech

database. There are 8 speakers, labeled from S1 to S8. The vocabulary of digits is used in

speaker recognition system. Users had to speak a code in order to gain access. By checking

t he voice characteristics of the input ut terance, using an automatic speaker recognition, the

system is able to add an extra level of security.

M icroprocessor Based Multiple Process Variable (January 2010 – May 2010)

A control system is designed to continuously monitor temperature, pressure and level for a

boiler with a 8085 at i ts heart acting as a digital controller, with A/D and D/A,

A mplifying/Scaling interfaces with the t ransducers and actuators.

A H igh Efficiency Audio Amplifier Based on a Monophasic Inverter ( May 2009)

An audio amplifier was simulated, designed, built and tested, based on a switching

technique, by means of a monophasic inverter. Variable width pulses control the

monophasic inverter switching. The duration of each pulse was established by comparing

t he input (reference signal) and a sample of the amplified output signal, the difference

between both produces the error signal that determines in real time the pulse width. A

lowpass fil ter was connected to the inverter output the principal function of which was to

eliminate the high frequencies due to the inverter chopping.

Decoding Of I nfrared Remote Control Software ( May 2008)

This Infrared Remote Control Software project based on M icrochip 16C57 microcontroller is

a reference guide to decode infrared remote control signals from television, VCR, air

conditioner or other home appliances handset that uses NEC 6121 infrared format. Once

one is able to understand how to decode an IR signal of a certain format, decoding another

format can be easily done as the f low chart is more or less the same except the t iming of the

new format.

16 bit processor is w r itten in V HDL (April 2007)

A fully functional and synthesizable 16 bit processor is writ ten in VHDL, having key

features like, von Neumann bus architecture,16 bit instruction core,16 bit data path,20

i nstructions,4 clocks per instruction,25 M IPS

Aerial Robot (October 2006)

A four rotor RC helicopter is built from scratch for a Technology Exhibition Competition for

f resher.

Hobbies & I n te rests:

Sports and adventures: Motorcycling, Cricket, Soccer, Swimming

Music and Arts: Instruments (guitar, f lu te, keyboard and tabla), Vocal (Hindustani

C lassical), Poetry

Contact this candidate