Engineer Electrical

FAISAL AZAM

***** ****** ***, ************, **-**660 ■ (Cell) 512-***-**** ■ ********@*****.***

SUMMARY

A semiconductor device characterization engineer with 13 years of experience in foundry business and

extensive knowledge of physics and process. Job function is dynamic and highly demanding in nature.

PROFESSIONAL EXPERIENCE

Samsung Austin Semiconductor Austin, TX 2007 – 2013

Logic and Memory Integration – Device Engineer

Drive transfer of new Logic and Flash memory technologies to manufacturing, 32nm node and beyond

Work closely with Quality and Process teams to achieve new product qualifications

Analyze in-line, fab-out and failure analysis data to establish key relationships between processing and

device/yield/reliability impact. Improve process capability (Cp, Cpk) and performance (Pp, Ppk) metrics.

Lead cross functional development projects in order to optimize device characteristics

Write D OE for FEOL and BEOL process improvement and evaluate effect on yield, performance,

reliability of the product. Member of process change control board.

C onsult innovative ways of test optimization and early fault detection

Electrical spec ownership. Ensure compliance and provide disposition of non-conforming products.

Use H P parametric analyzer, Agilent functional tester to run standard and bench tests as needed

Par ticipate and coach at cross-department techonology forums and seminars

IBM Fishkill, NY 2000 – 2007

Electrical Characterization Engineer

Analyze chip functionality data to qualify several advanced CMOS logic and eDRAM products. Use

troubleshooting skills to drive corrective actions for manufacturing yield issues.

Track progress of the product from post tape-out through ramp up until release to production

As a member of cross unit/Alliance team, present weekly data summaries, trends, data correlations

and develop new modes of analysis as needed to delineate root cause

Establish quality control limits and metrics in order to optimize yield and performance objectives.

Issue documents and procedures on chip testing protocols. Write test instructions for Agilent testers.

Work closely with Test, Design, System Engineers, Wafer Fab, QA, FA and Manufacturing to ensure

technology meet performance, yield, variability and reliability objectives

Perform joint development work with AMD, Sony, Toshiba, Chartered to meet fabrication objectives

Digital Equipment Corporation Hudson, MA 1995 – 1996

VLSI Design Engineer (Co-op)

Member of Alpha microprocessor circuit design team

D esign I/O circuit and 64bit MUX

U tilize SPICE software in clock grid, power consumption, critical path and timing analysis

EDUCATION

Rensselaer Polytechnic Institute Troy, NY May 2000

MS Electrical Engineering. GPA: 4.0/4.0

University of Cincinnati Cincinnati, OH June 1998

BS Electrical Engineering. GPA: 3.81/4.0

PATENT: Systems and Methods for Overlay Shift Determination (# US 7,084,427 B2)

AWARD: ”Best of IBM” award recipient in 2007 for demonstrating focus & passion for work

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