VLSI, Verilog HDL, Digital Design

RESUME

D.KISHORE KUMAR

Plot no **

Near keshavareddy concept school,

Kalvakunta road, sangareddy Medak Dist

A.P- 502001 Contact No: 917-***-****

India. Email:

***********@*****.***

CAREER OBJECTIVE

To be associated with a progressive organization which can provide me

a dynamic work sphere to use my inherent skills to hone my aptitude for

the organization objectives and my career in the process.

ACADEMICS

. Pursued Masters of Technology (M. Tech) from B.V.Raju institute of

technology affiliated to J.N.T University with a specialization of

VLSI SYSTEM DESIGN, with 80.44% and passed out in 2012.

. Pursued Bachelor of Engineering (B.E) from Vasavi College of

Engineering affiliated to Osmania University, in a stream of

Electronics & Communication Engineering and passed out in 2009 with an

aggregate of 70.01%.

. Pursued Intermediate from Board of Intermediate, at a discipline of

Maths, Physics & Chemistry and passed out in 2005 with an aggregate of

94.8%.

. Pursued SSC from Zilla Parishath High School, Andole and passed out in

2003 with an aggregate of 84.6%.

TECHNICAL SKILL SET

. Expertise in Digital design

. Expertise in Verilog HDL

. Programming Languages: C.

. Expertise in 1. Cadence RTL Compiler

2. Xilinx ISE

TRAINING

. Undergone Training on "Advanced Digital Design" in CITD for 3 months

during Oct 2012 to Dec 2012

PUBLICATIONS

. Presented a journal on "Modified Architecture of Vedic Multiplier for

High Speed Applications" in

International Journal of Engineering Research and Technology, ISSN no:

2278-0181 Vol 1, Issue 6, Aug 2012.

. A paper on "A Novel Approach to Proposed Vedic Multiplier for High

Speed and Area Efficient Applications" is accepted for Publication in

IJCA ONLINE Publications in Dec 2012.

EXPERIENCE

. Working as a VLSI Trainee Engineer in magnify technologies since July

-2012;

PROJECTS HANDLED

1. Design of High Speed Multiplier Using Vedic Mathematics

Language : Verilog

Software Used : Cadence RTL compiler

Description :

Vedic Mathematics is the ancient methodology of

Indian mathematics which has a unique technique of calculations based

on 16 Sutras (Formulae). A high speed and area Efficient multiplier

design using Vedic Mathematics is presented in this project. The idea

for designing the multiplier and adder subtractor unit is adopted from

ancient Indian mathematics "Vedas". On account of those formulas, the

partial products and sums are generated in one step which reduces the

carry propagation from LSB to MSB. The implementation of the Vedic

mathematics and their application to the complex multiplier ensure

substantial reduction of propagation delay in comparison to

conventional Multipliers.

2. Designing Efficient Codec's for Bus-Invert Berger Code for Fully

Asymmetric Communication

Language: Verilog

Software Used: Xilinx ISE

Description:

Berger-invert code is a coding scheme proposed

recently to protect communication channels against all asymmetric

errors and to decrease power consumption. Bus-invert coding is a

method intended to reduce the power consumption or switching noise in

a bus .It uses one extra bus line, called bus-invert, to inform the

receiver side whether a current pattern is inverted or not. The signal

BI can be generated as a function of either the Hamming weight of a

pattern w(D) or the Hamming distance between the present pattern.

PERSONAL PROFILE

Name : D.Kishore kumar

Date of Birth : 19-03-1988.

Gender : Male.

Marital Status : single.

Nationality : Indian.

Languages known : English, Hindi, Telugu.

DECLARATION

I hereby declare that the information furnished above is true to the

best of my knowledge and belief.

Date:

Place: D.Kishore

kumar[pic][pic]

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