Design Signal Processing

BHAVYA ROOPA NALLAMALA

Email: ***********@*****.*** 2400 Waterview Parkway,#731

Phone: 469-***-**** Richardson, TX 75080

OBJECTIVE

Seeking an entry level position in the field of Integrated Circuit Design, Testing and Validation.

EDUCATIONAL PROFILE

Master of science in Electrical Engineering December 2013

The University of Texas at Dallas, Richardson, Texas GPA: 3.54

Bachelor of Technology in Electronics and Instrumentation Engineering May 2011

Jawaharlal Nehru Technological University, Hyderabad, India GPA: 3.9

TECHNICAL SKILLS

Programming Languages : C, JAVA, PERL Scripting

Hardware Description Languages : VHDL, Verilog HDL

EDA Tools : HSPICE, Cadence Virtuoso Suite, Synopsys Suite, Xilinx ISE,

ModelSim, Micro Magic MAX, MMI-SUE

ACADEMIC COURSES

VLSI design Advanced VLSI Design Analog IC Design

Advanced Digital Logic Testing and Testable Design Computer Architecture

Digital Design through Verilog Active Semiconductor Devices Digital Signal Processing

INDUSTRIAL EXPERIENCE

IC Design and Verification Intern, Tezzaron Semiconductors (Sept '12 - Dec '12 & June '13 - Aug '13)

Worked on the layout design for 3D DRAM stacks. The project involved designing of a memory module

which has 32 ‘64GB’ 3D memory stacks.

Involved in the analysis and physical design of complex supporting circuits such as Sense Amplifiers,

Decoders, ECC using 40nm technology.

Worked on physical verification including DRC/LVS and parasitic extraction for parts of this high -

density memory circuit.

Duties included RTL Schematic Design, Layout optimization and verification, Routing and Floor

planning. The tools used are from Cadence and Mentor Graphics.

ACADEM IC PROJECTS

Placement and Routing of a 16 bit ALU using generated library in CADENCE (IBM 130nm)

The 16 bit ALU is coded in Verilog and is synthesized using Synopsys Design Compiler to generate the

mapped netlist.

Designed basic combinational and sequential gates using Cadence 130nm node and generated a new cell

library using Liberty NCX.

Placement and routing of the final layout is done using Cadence Encounter.

Static timing analysis is done using Synopsys Primetime.

Full custom design of SRAM (IBM 90nm)

Designed a 512 bit 6T SRAM using Cadence Virtuoso.

Addressed memory cell Read stability and writability issues through proper transistor sizing.

Constraint - Area vs Delay optimization through custom layout.

Results showed a worst case read time of 440ps, write time of 222ps and area of 3.15sq.um/bit.

Design of 2 stage Operational Amplifier

Designed a two stage operational amplifier using 0.35um CMOS process and achieved unity gain bandwidth

of 10MHz with differential gain of 85dB and power dissipation of less than 0.3mW.

Performed Slew Rate, CMRR simulation to validate the design.

Design of Error Correction Code Schematic using Hamming Code Approach

32 bit ECC circuit is designed using Cadence circuit design tool.

Circuit corrects any single-bit error and automatically produces ECC bits for any 32b word. Output is

analyzed using CosmoScope.

Exploring Synopsys synthesis and test tools to implement Testable circuits

Used Synopsys tool set to model and design digital circuits and then the designs are imported into

TetraMAX tool to find all stuck-at faults, the test vectors and the fault coverage.

Design for Testability (DFT)

BIST: A 4-bit comparator is made BIST testable by adding an 8-bit External-XOR LFSR, a pseudo-

random pattern generator and 4-bit MISR as signature compressor. This system is controlled by normal/test

pin alone.

Scan chain Insertion: A 4-bit up/down counter is designed using D flip-flops. Here the normal flip-flops are

replaced with scan Flip-flops to build a scan chain. Area and timing analysis is done for both the cases and

the total cell area is seen to increase for the case with the scan cell insertion.

Cache Design Optimization of Alpha 21264/EV6 Microprocessor

The Cache parameters such as Cache levels, Unified vs Split, Cache Size, Associativity, Block Size and

Block Replacement Policies are varied for 4 benchmarks of the Alpha microprocessor.

PERL script is used to simulate the various possible combinations of these parameters.

CPI vs COST analysis is done.

Design choices are made accordingly and cost function is defined through which optimal configuration of

Cache design is found.

Analysis of different Branch Predictor types and Various RAS Configurations

The Effect of different choices of the branch predictors for the given Apha 21264 processor is analyzed.

The performance of different RAS configurations and the branch predictors is explored by plotting graphs

against CPI values and branch predictor hit rates provided by the simulator.

HONORS

“Sri Kode Venkatadri Chowdary Gold Medal”, VNR VJIET (JNTU), conferred to the best out going student

during Under Graduation.

“VNR VJIET Student Merit Scholarship Award” for consistent Academic Excellence.

PRATHIBHA Scholarship Award and Gold Medal for Academic excellence in schooling by the Govt. of AP,

INDIA.

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