Engineer Design

GLENN C. JACKSON

● **** Kandy Drive ● Austin, Texas 78749

● Home: 512-***-**** ● ab4ofj@r.postjobfree.com

Job Objective: Applications Engineering, Documentation, Training/Technical Support

Key skills include:

Embedded Product Support Tier 1 Customer Training/Support Creation of Technical Papers

Debug with Lab Equipment Design Project Management Schematic Reviews

Debug Lab and Spice Simulation WW Sales/Marketing Campaigns Contract Review/Negotiation

PROFESSIONAL ACCOMPLISHMENTS

● Resolved Tier 1 customer development issues including debug of embedded hardware and

software for various OS environments

● Created C, C++, Assembler code for embedded SOC peripherals (USB,LCD,Audio,etc.)

● Designed micro Processor circuits with EDA tools (VHDL,Verilog,Synopsys,DA)

● Created and used MCSPICE models for cross talk design rules.

● Created and used MCSPICE models for timing modeling and verification.

● Lead hardware design engineer for multiple embedded modules

● Technical lead of Worldwide rollout of Motorola M.CORE architecture

● Created, published, and presented application notes, articles, and training courses for processors

(ex.: PowerPC, i.MX, TI OMAP35, TI Sitara, Marvell PXA270/PXA3xx) and embedded peripherals

(ex.: LCD, Audio [I2S, AC’97], DDRx SRAM, UART, PMIC)

TECHNICAL SKILLS

Software: Microsoft Office, Salesforce/Siebel customer support, Framemaker, Unix, Solaris, Linux, C, C++,

Assembly, Hardware debug and simulation tools for various architectures

Lab equipment: Logic Analyzers, Teradyne, MAC, Temptronic

PROFESSIONAL EXPERIENCE

Logic Product Development

4/2008 to 8/2012

Applications Engineer

● Supported customer development of SOC embedded products

● Created support documentation and software suites including schematic reviews, application

notes, user guides, Linux Virtual Machine for Windows user guide.

● Created and integrated FAQ system into the LogicPD website

● Project lead for Application Group transfer to new customer support system (SalesForce) Focus

on system “look and feel”, training, and scheduling of cross over

● Trained new hires and interns on technical issues and customer support

Marvell Semiconductor

12/2006 to 12/2007

Senior Applications Engineer

● Supported Tier 1 pre sales and customer support for embedded systems

● Tech Lead of PXA270 transfer from Intel to TSMC foundry

● Resolved AE customer issues, schematic reviews, and product support for PXA27x and PXA3xx

mobile and embedded products(LCD,I2S,AC'97, SSP,DDR SRAM, PMIC)

● Managed customer resolution tracking (Symplicity) for the AE group (Worldwide)

● Wrote application notes and Development Manual review for technical accuracy

StarCore DSP, LLC

2/2006 to 8/2006

Applications Engineer

● Created integrated core demos with StarCore SC140 and ARM926EJ S core

● Generated cache profiler analysis with DSP “VLES” (VLIW) instructions

● Provided in house beta IDE tool testing and feedback

● Resolved customer questions using internal StarTrack system

Energy Homes

4/2005 to 9/2005

Project Coordinator

● Scheduled and Supervised construction project activities

● Charted construction cash flow and scheduling of all projects, with SQL tools

Motorola/Freescale

2000 2004

Senior Applications Engineer

● Generated assembler and C application code for ARM and PowerPC architecture with Metrowerks,

Green Hills, Wind River (Diab Data), and P&E Gnu

● Supported pre sales for PowerPC (MPC500 & MPC5500) embedded processors

● Performed lab Verification of uProcessors with Teradyne, MAC, Temptronic machines

● Created and Delivered technical presentations, training classes, product briefs, design memos,

articles, and application notes

● Resolved & Communicated vendor and customer problems for tools and products

● Directed and Supervised interns and rotational engineers

1997 1999

Technical Marketing & Systems Development Engineer

● Technical Lead for worldwide roll out of M.CORE architecture including Evaluation Kit, training

courses, assembler/C App code, product briefs, and marketing folders

● Lead Engineer for support of M.CORE Code Compression code and training

1989 1997

Design Engineer

● Designed circuits with EDA tools (VHDL/Verilog/Synopsys/DA) for Bus Interface Units, Pad Ring,

Arbitration, and Interrupt modules

● Created MCSPICE models and timing tests for verification of (PowerPC, 88110) buses

● Created Verification plan and Test Bench code for group development (PowerPC500)

● Directed and Scheduled work of LIMB module team and USB 2.0 integration team

VPI&SU (Virginia Tech)

1988 1989

Lab Technician

● Maintained Thick Film Lab and equipment

● Created Thick Film Lab circuits from layout & photo, to final test

U.S. Gypsum Inc.; Norfolk, VA

1987

Project Engineer (Intern)

● Created and revised plant drawings for upgrade/maintenance projects

● Generated boilerplate contracts with outside contractors

EDUCATION

Graduate Course, Computer Architecture, University of California (Berkeley, CA) 1992

Graduate Course, Computer Arithmetic, University of Massachusetts (Boston, MA) 1991

Bachelor of Science Electrical Engineering (BSEE), Virginia Polytechnic Institute and State University, (Blacksburg, VA)

1989

Bachelor of Business Administration, Finance (BBA), College of William and Mary (Williamsburg, VA) 1982

PROFESSIONAL PUBLICATIONS

Patent Application:

“Multiplexor Test Structure.” Motorola Number #SC02090A. January 1994

Paper Presentation:

“Advantages of Code Compression in Engine Control” Engine Expo 2001, Stuttgart, Germany. June 2001.

Articles:

“Compression Squeezes Code Into Less Memory.” Embedded Developers’ Journal. September 2001

“A 66MHz Configurable Secondary Cache Controller with Primary Cache Copyback Support.” Digest of Technical

Papers of the 1992 IEEE Symposium on VLSI Circuits. June 1992. Co Author.

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