Design Electrical Engineering

J ing Gao

Address: ****E Melody Lane Phone Number: 602-***-****

City, State, Zip Code: Gilbert, AZ 85234 Email address:******@***.***

Personal Profile

New-Grad Master in Mixed-signal Circuit Design area actively seeking a full-time job focus on Analog and Mixed-

signal Circuit Design, strong background on CMOS, analog and digital circuit design, Nyquist ADC, sigma-delta

ADC and DAC, familiar with high-speed I/O and PLL, and two years’ experience with Cadence design and Virtuoso

verification and extraction.

Education

Master of Electrical Engineering, Arizona State University, Tempe, AZ Graduation: May, 2013

GPA: 3.68/4.00

Bachelor of Electrical Engineering, Huaihai Institute of Technology, China Graduation: June, 2011

Ranking: Top 5 out of 110

Lab Experience

Design A Macro-model of A Fully Differential RSD-Based Pipelined ADC In Cadence Jun 2013

● Requirements: Design a 12-bit RSD based pipeline ADC in Cadence, sample rate is 80MHz, input bandwidth

is 39MHz or less, 1Vpp differential and supply voltage is 1.8V.

● Results: 9 1.5-bit RSD stages and 1 3-bit flash ADC stage make up a 12-bit RSD pipeline ADC, SNDR of

simulation is 71.1692dB and ENOB is 11.53.

Modeling And Simulation of A Second Order Continuous-time Sigma-Delta Modulator Dec 2012

● Requirements: Design a macro-model of a fully differential second order continuous-time sigma-delta

modulator in Cadence. Signal bandwidth is 200 KHz, sample frequency is 40MHz or less, minimum SNR is

70dB, maximum input signal level is 0.5Vpp differential and supply voltage is 1.5V.

● Results: Choose OSR=80, sample frequency is 32MHz, 2-bit quantizer, 2-order CIFB structure to achieve

the SNR requirement, SNR of simulation is 80.27dB.

Engine Controller For A 12-Cylinder 6-Speed Car (Group project) Apr 2012

● Requirements: Design a circuit to control the 12 cylinders and gears of a car. The circuit includes inputs

block, auto-pilot diagram turn-on decision block, RPM/gear control block and cylinders/gears block. I am

responsible for part of RPM/gear control block.

● Results: For the car goes down a ramp, control the cylinders and gears according to the logic given to

maintain the same speed. Mainly use adders, sub-tractors, comparators, multipliers, MUXs and dividers.

VLSI Phase-Locked Loop Circuit Design (Group project) Dec 2012

● Requirements: Design a PLL which is programmable to two frequencies for HS-G2(A/B) applications with

0.18um TSMC technology. Input reference clock at 26.00MHz, output clock at 2.496GHz/2.912GHz, 1MHz

bandwidth. PLL includes PFD, LPF, VCO and frequency divider. I am mainly responsible for frequency divider.

● Results: Use AND, OR, FF and Inverter to form programmable frequency divider which can divide 96 and

112 correctly.

Rail To Rail Amplifier Design Mar 2012

● Requirements: Design a rail to rail differential amplifier with TSMC 0.25um technology. Given supply is 3.0V,

maximize the input common mode range, DC gain more than 40dB, unity gain frequency is 80MHz or more

with CL=1pF, power less than 1mW.

● Results: Simulation result are CM input range is 0-2.8V, DC gain is 40.07dB, and unity gain frequency is

80.19MHz.

GSM900 Direct Conversion Front-End Receiver Design Apr 2012

● Requirements: With the TSMC 0.35um technology, for 900MHz, required sensitivity is -104dBm, IIP3 is -

12dBm, NF is between 7.5dB-8dB and current is less than 1mA.

● Results: Overall performance of 24dB Gain, 4.6dB NF, -10dBm IIP3, 40mW power consumption using LNA,

Gilbert cell mixer and inter-stage impedance matching network.

Core Courses

Analog Integrated Circuit, Adv Analog Integrated Circuits, Analog to Digital Converters, Oversampling Sigma-Delta

Data, Digital System Circuit, VLSI Design, Serial Links, Power Electronics, Comm Transceiver Circuit Design

Contact this candidate