Engineer Design
Resume:
Benjamin Russell
ab3s3s@r.postjobfree.com
Midlothian, VA, 23113
OVERVIEW
Microprocessor automation engineer with seven years of experience
working on cutting edge technologies and methodologies. Focus areas include
initial placement, post-routing optimization and verification. Experience
as the team leader of distributed, international group.
TECHNICAL AREAS OF EXPERTISE
. Communicating technical details to customers.
. Project management of defect and development requirements.
. C, C++, C#, Java, Perl, and Tcl programming languages.
. Maintaining and debugging construction, placement and timing
verification tools.
. Characterizing and debugging standard cell libraries.
. Devising, running and verifying quality regressions.
. Experienced in using a standard design flow, from HDL to a placed,
routed and verified OA layout.
. Linux, Unix and Windows system administration.
WORK EXPERIENCE
IBM, System and Technology Group, Electronic Design Automation
Advisory Engineer/Scientist (October 2012 - Present)
. Gate Level Timing Sign Off (GLSO)
o Supplied primary support for customers of the GLSO environment for
the POWER 7, POWER 7+, POWER 8, Zgryphon+, Z360 and Oban
processors.
o Responsible for updating the design methodology to allow gate level
timing abstracts to function with arbitrary input, allowing for
cross-unit, cross-chip and cross methodology logic reuse.
o Played a lead role in the introduction of a novel means of
verifying the quality of a boundary, or black-box gate level timing
abstract, enabling chips to time globally with boundary abstracts
at a significant runtime savings.
. Routing Aware Physically Incremental Driven Synthesis (RAPIDS)
o Provided support for customers of the RAPIDS environment for the
Z360 and POWER 9 processors.
o Scientifically determined optimal detail router parameters for a
host of criteria.
Staff Engineer/Scientist (May 2009 - October 2012)
. Gate Level Timing Sign Off (GLSO)
o From 2011 to present assumed a project management role to oversee
bug fixes and new feature development for the GLSO environment.
o Played a lead role in the introduction of a novel gate level design
verification flow. Allowed for a dramatic reduction in run time and
memory necessary to verify that a design meets all requirements,
including nominal and best case timing, noise, electromigration,
power and design rule restrictions.
o Developed a method to verify that synthesized block timing
abstracts accurately represent the network they are based on.
o Developed a method to audit that a timing, noise, electromigration,
power or electrical check simulation has met necessary parameters.
Engineer/Scientist (January 2007 - May 2009)
. Standard circuit library characterization
o Responsible for the characterization and verification of the
standard cell delay rule library for the POWER 6, Z6, POWER 7,
Zgryphon, and Blue Gene Q processors.
o Improved the characterization methodology for latch and clock
buffer cells to better model equivalent transistor level simulation
timing.
o Maintained and improved a set of quality of results verification
tools.
. Transition to industry standard circuit library characterization
o Played a lead role in the transition from IBM internal to industry
standard library characterization methods. The rule format was
changed from Delay Characterization Models (DCM) to liberty rules,
and the delay tables were changed to include electrical current
source modeling. This involved both establishing the new
characterization environment, performing the necessary simulations
and verifying continued levels of quality as compared to alternate,
transistor level timing environments.
Naval Research Laboratory, Space Applications Branch
Engineering Internship (May 2005 - August 2005)
. Created a Signals Analysis package to monitor the continuing performance
of experimental Cesium clocks and Mazers for use in GPS applications.
. Worked as part of a team to analyze a new vendor supplied GPS Receiver.
. Upgraded a system to continually monitor long running experiments.
. Screened and approved for a Top Secret security clearance.
Baylor College of Medicine Cognitive Neuroimaging Laboratory
Programmer and Lab Assistant (May 2002 - August 2004, Contract Work through
2007)
. Assisted with the experimental design and implementation of cognitive
tasks as well as database solutions for later analysis.
. Assisted with the experimental design and implementation of tasks to
evaluate the long term effect of closed head injuries in children.
. Administered tests to both research subjects and patients.
AWARDS RECEIVED
. IBM Outstanding Contributor Award, 2013
. IBM "Bravo" Award, 2010, 2008
. Professional Review: Top Contributor: 2013, 2012, 2011, 2009
. Professional Review: Above Average Contributor: 2010, 2008
EDUCATION
University of Colorado at Boulder - M. E. in Electrical Engineering,
Expected Class of 2014
Degree in progress via the CAETE distance learning program.
Rensselaer Polytechnic Institute - B.S. in Computer and Systems
Engineering, Class of 2006
Minor in Computer Science
RELEVANT COURSEWORK
. Advanced Computer Architecture, Computer Hardware design, Advanced
Computer Hardware design, VLSI design, Analog IC design
. Distributed Systems, Database Systems
. Software Engineering for Stand-alone systems, Software Engineering for
Concurrent Systems (Project development best practices from Requirement
Elicitation to Implementation)
. Real Time Embedded Systems, Real Time Digital Media
. Computer Performance Modeling
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