Design Engineer

SHANMUKHA REDDY MANDHA

AM BICHL ** • **** •VILLACH •KARNTEN • AUSTRIA •

*********.******@******.**

*********.******@*****.*** • +43-660*******

Details-focused professional with M.S. in Micro Electronics (Electrical Engineering) eager to offer strong academic background, as well as knowledge gained from multiple research / instructional roles, toward maximizing an employer’s success.

PROFILE OF QUALIFICATIONS

• Knowledgeable in Digital design, Analog design, Testing of an IC, System-On-Chip study and Sensor Design.

PROFESSIONAL EXPERIENCE

• Organization : Technical University, Graz,Austria

• Designation : Researcher(working at Infineon Technologies)

• Duration : September 2011 – till date

• Project description

1. I am working as researcher at TU,GRAZ. And my place of work is Infineon technologies,Villach. Currently I do Analog Mixed design verification of ADC’s. I also do design verification of IVR, Die Temperature Sensor, Oscillator and Multi ADC’s using Titan(Analog Spice Simulator), Modelsim, HSPICE, COMPASS and AVENUE(Analog Verification) at Infineon technologies. COMPASS, Titan and Avenue. are the tools internal to Infineon technologies.

2. During my Masters program I took a course on RF concepts during which I designed a 2.5GHz sub-rate sampling system used in high-speed transceivers using cadence environment AMS HITKIT 0.35um.

• Organization : Sankalp Semiconductors, India

• Designation : Design Engineer(IO Design team)

• Duration : November 2010 – August 2011

• Project description

1. Under went knowledge project in design verification of LVCMOS_18 and LVDS IO’s

Duty cycle distortion(DCD) measurements, MC Simulations and debugging methodology are done in Spectre

Result post processing is done using OCEAN scripting

2. Worked on analog layouts for Max Linear Company in 65nm,CSM technology

I have done layouts for blocks like voltage regulators(taking EM into consideration), ADC’s, Individual digital and analog blocks. Also was part in developing LVDS IO(IP project) layout in 45nm, TSMC technology

3. Worked on automation of Liberty files (synopsys) using Perl

4. Learnt Cadence’s SKILL which helps automating layout

5. SRAM memory characterization (SPREG) in 28nm technology

EDUCATION AND RELATED COURSEWORK

Master of Science in Engineering (Micro Electronics) (Graduated 2010,March) CARINTHIA UNIVERSITY OF APPLIED SCIENCES

Bachelor of Technology in Electronics Engineering (Graduated 2007) JNT UNIVERSITY

Fabrication & Packaging Technology of IC • CAD tools • Design of Analog Integrated circuits • Design of Digital Integrated Circuits • Advanced Topics in Analog Integrated Circuits • System Modeling and Verification • System-On-Chip Architectures • Testing of Integrated Circuits • Integrated Data Converters • Integrated Sensors for Automotive Applications • Design of High Performance Analog and Mixed Signal Integrated Circuits • Advanced Topics in Digital Integrated Circuits • Physical VLSI Design • Microprocessors & Microcontrollers • C & Data Structures • RF Electronics • Control systems •

Associate Engineer Intern, RESEARCH CENTRE IMARAT (RCI), HYDERABAD, INDIA 2006 – 2007

• Utilized broad scope of engineering knowledge to participate in the project modeling of a programmable 8254 timer employing VHDL coding language developed to resolve common timing problems in microcomputer system design.

• Achieved 8254 megafunction programming to match requirements by administering one of the desired delay counters.

• Instrumental in initiating application on “on-board computers” (OBCs) for attaining perfect missile functioning.

SKILLS PROFILE

Masters’ Thesis, Carinthia University Of Applied Sciences, Villach, Austria 2009-2010

CORDIC Based Equalizer Coefficients Calculation Unit

I had worked on “CORDIC based Equalizer Coefficient Calculation Unit” at Carinthia University of Applied Sciences (Fachhochschule),Austria in collaboration with austriamicrosystems AG, Graz, Austria. CORDIC Based Equalizer Coefficients calculation Unit (thesis) was pursued in VHDL is one of the challenging task in the field of audio world. Minimum possible area, gate count, comparison of the designed calculation unit in VHDL with that of Matlab model are the main tasks of this thesis. Synopsys, Modelsim, Matlab are the different tools used while working on the thesis.

Masters’ Projects,Carinthia University of Appled Sciences, Villach,Austria

Invented, developed and modeled groundbreaking digital, analog and system on chip capable of utilization and function in many facets of corporate electronics engineering. Conceptualized, Created new technology gaining academic recognition in areas of innovation and design. AMS HITKIT 0.35μm CMOS technology is used.

Digital Design:

• Design of 5-bit Flash ADC( synchronization, thermometer to one hot coding and one hot to binary coding)

• Simulation, Synthesis and Layout of the Multiplier designed using VHDL. Synopsys for synthesis and Encounter for the layout are the tools used

• Design of RISC Core processor including the synthesis

• 1024*8 bit SRAM design with 6 Transistor cell with full custom layout

• Exploited the difference between full adder architectures

Sensor Design:

• Design of Temperature Sensor with differential stage. Performance, area gain, temperature dependence and the gummel plot are the parameters studied in cadence spectre

• Design of Hall Sensors that allows the simulation of chopped hallplate and the simulation of the parasitic capacitance of the n-well junction (hall resistor) in cadence spectre

• Design of accelerometer sensors in simulink (linear versus non-linear model)

• Design of pressure sensors in cadence spectre

Analog Design:

• Design of 2.5GHz sub-rate sampling system used in high-speed transceivers. Utilized Cadence Environment AMS HITKIT 0.35um.

• Design of Switched Capacitor Comparator (analog design and full custom layout).

• Design of 5-bit flash ADC. It Comprises of SC-Comparator, Resistive ladder, Latch, Output register.

• Design of a fully differential OP-AMP including the biasing circuit.

System On Chip:

• Understanding machine language and assembly flow by reverse engineering through Instruction set architecture(ISA)

• Pipelined execution and hazard resolving techniques with respect to coffee RISC core processor

• Network-on-Chip (NoC)- Routing, Buffering and Flow control are the parameters studied.

• Study of Coprocessors.

Testing of an IC:

• Design of 5-bitflash ADC(digital part). The design is simulated and synthesized with insertion of scan possibility

• Implementation of Built In Self Test(BIST) for ROM

TECHNICAL PROFICIENCIES

Technical Skills: RTL Design • Analog Design• Digital Design

Languages: C • Verilog • VHDL • VHDL-AMS(basic) • SKILL • Perl

Operating Systems: Unix • Macintosh

Design Tools: Cadence – design frame work tool, Layout Encounter • Calibre • Synopsys – Design Compiler • ModelSim • MatLab • Titan(Analog Spice Simulator) • Avenue(Analog Verification Environment) •HSPICE

Microsoft Office • Microsoft Visio

CERTIFICATIONS AND ACHIEVEMENTS

• Was Indian students representative at Carinthia University Of Applied Sciences

• VHDL and Verilog Certification from UTL technologies

• Got placed in Indian Air Force as flight lieutenant

• Was an event Coordinator at MICROCOSM, a national level symposium conducted by ECE dept. MGIT

REFERENCES

• ********.******@******.**

Univ.-Prof Dipl.-Ing. Dr.Wolfgang Bosch

Head of the Institute

Graz University of Technology,Austria

• FH-Prof. Dipl.-Ing. Erwin Ofner and vice dean

*.*****@**-********.** / *.*****@***.**.**

• Dr. Dipl.Ing. Johannes Sturm, Professor in analogue design

*.*****@**-********.**

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