BRIAN TAHAMZADEH

***** *** ****** **, ******* Viejo, CA 92692

TEL: 949-***-****, Cell: 949-***-****

Email: ab3k4n@r.postjobfree.com

OBJECTIVE: To secure a challenging H/W signal integrity, EMI test or

validation Test Engineering position in the field of electronics or related

area with a company that will offer growth and make effective use of my

hands-on training.

EDUCATION:

BS/EE Electrical Engineering, May 1985.

Test Equipment: Oscilloscope, Frequency Counter, Vector Network Analyzer,

Spectrum Analyzer, PCIe, USB2.0 & 3.0 Bus Analyzer, Data & RF Network

Analyzer / Generator, JBERT and AWG Tester. TekExpress & SerialExpress MOI

package (HP and Tektronix). Serdes & PHY qualification for SATA, SAS 6G,

PCIe and USB3.0, USB-IF & HDMI compliance testing. Familiar with I2C,

JTAG, SPI, UART, SCPI, VISA, GPIB, RS-232, CAN, USB, ARINC, LAN interfaces.

ICT (In Circuit Tester) HP3070, GenRad, ATE Agilent 7000, Teradyne and

Labview Teststand. Computer Knowledge: Programming in C & C++, Visual Basic

and Labview10.0, Good Understanding of UNIX, LINUX, Windows XP, VISTA and

Winodws7/8. ORCAD/CADANCE, schematic capture, PCB layout PI & SI, EMI

simulation.

EMPLOYMENT HISTORY:

MEGGITT-INC, Corona CA.

Feb 2013 - July 30, 2013. Contract, 3 months, Job Title: EMC Test Engineer

Consultant

Duties: Working closely with H/W design team to get EMC certification for

PSC (Pneumatic Control System) unit. RTCA-D160-F Standard using ARINC -429

communication protocol using outside test lab. Test for Magnetic Effect,

Power input, Voltage Spike, Induced Signal Susceptibility, RF Emission,

Lightning Susceptibility, Pin injections and ESD tests. Run HALT and Shock

environmental tests.

STEC-INC, Santa Ana CA.

May 2012 - December 2012. Contract, 6 months, Job Title: Design

Verification Test Engineer Consultant

Duties: Working closely with H/W design team for new or existing SSD (Solid

State Disk), (PCIe, SAS, uSAS, SATA and Fiber channel drives) 8-16 channels

up to 6Gig data rate. Complete Serdes/PHY interface qualification on new

SOC controller for SAS and PCIe interface drives. DVT test and verification

for user interface, power consumption, power supply regulator efficiency

testing, in-Rush current, Hot Swap controller function and Vback charging.

Use IOMETER for performance testing. Full signal integrity compliance

testing using JBERT Test setup for 3G & 6G for TX/RX sensitivity testing.

Flash memory output drive strength setting using Lauther bauch JTAG

interface to generate memory Schmoo plot. Labview, 8-Corners Automation

improving the product performance to meet all the compliance requirements.

Pace America PLC, El Segundo CA. April 2011 - April 2012. Laid Off

Job Title: Sr. Hardware Reliability Test Engineer

Duties: Working closely with H/W design team for new or existing DVR set

top boxes to find any design, EMI/EMC or manufacturing related issues on

Power supply, mainboard and peripherals. Run failure analysis on return

units for any reliability and quality issues down to component levels. Work

closely with part vendors to monitor their failure rate and improving their

test process. Work closely with manufacture test engineers to improve their

test methodology. Work closely with DirecTV engineers regarding their field

failure units to find the root cause of the issue. Brown-out, power glitch

and power cycle test using test automation on Agilent AC power source

6814B. Coordinate signal integrity, Reliability, EMI/EMC and Labview

Automation testing to improve the product performance to meet all the

compliance requirements. Run Full signal integrity compliance testing On

Broadcom, STMicro and Entropic SOC's for SATA, HDMI, USB, including RF

output levels. Work closely with customer related issues for design or

reliability related failures.

Western Digital Corp. Irvine, CA. June 2007- February 2011. Laid Off

Job Title: Sr. Principal Signal Integrity / EMI, Reliability Engineer.

Duties: Full Signal Integrity Analysis Serdes / PHY interface for SATA &

SAS 1.5/3.0 and 6Ghz drives, using Marvell and STMicro SOC controller,

including USB3.0, 5G high speed and SSD ( Solid State Disk, Flash Base

drives ). Validating Rx & Tx signals for RT-Eye and full Jitter

measurements (DJ, SJ & TJ). Measuring Return Loss for Near / Far End

sensitivity test using Agilent VNA and DCA6100A test equipment for S-

Parameter measurements. Working closely with PCB layout designers and EMC

engineers to verify proper PCB layout, stack up and trace routing for

differential pairs, including impedance matching to comply with EMC

radiated and immunity testing. Working closely with SRE (System Reliability

Engineering) team, to complete all system level Temperature cycle &

Shock/Vibration testing. Validate full signal integrity qualifications on

different range of OEM Servers, Mass Storage system, DVR, Satellite Set Top

boxes, Notebooks and desktop PC, using Tektronix TDS8000 and Agilent BERT

scopes. Full FCC, CE class A& B, EMI/RFI, Radiation / Immunity compliance

certification testing using in-house 3M and outside 10M Anechoic Chamber

labs for up to 30Ghz. Working directly on customer related issues inside

their chassis for EMI, SI issues.

Magtek Inc. Carson, CA. June 2004- May 2007. Position: Full time. Job

Title: Sr. EMC / Validation Test Engineer.

Duties: Take all new products to EMC Test Labs and debug all radiated and

conducted emission issues for FCC part 15, CISPR 22, class B

certifications. Fix any issues with USB and Ethernet interface ports.

Build and setup Pre-Compliance kit using Agilent E7405 Spectrum Analyzer.

Validate USB 1.1 & 2.0 (full speed / high speed ) using TDS7404 and USB2.0

software to measure eye diagram, chirp, J& K Tests, suspend, resume and

current tests. Check jitter measurements on D+, D-, differential lines,

plus rise and fall time. Using CATC, USB protocol Analyzer to debug

transaction issues. Full PCB layout, Signal Integrity/ EMC simulation using

CADENCE Allegro & EMSAT tools. Board level and system level MTBF, MIL-217 &

Bellcore reliability analysis using "items" software. Developed DVT

Reliability test and validation procedures for new products. Using Labview

for reliability test automation.

Balboa Instruments Inc. Tustin, CA. January 2003-July 2004, Position: Full

Time. Job Title: Sr. Mfg Test Engineer.

Duties: Generate board level ICT test program and test fixture design on

HP3070 ICT tester. Design functional test setup and develop test program

using National Instrument PXI, and Labview 7.1 to generate functional test

programs to test all Pool and SPA system control boards. Working closely

with manufacturing, and quality engineers to improve board level and system

level yield, product quality. Working with H/W engineers for NPI design

cycles, full DFT & DFM related issue on new and existing products.

Irvine Sensors Corp. Costa Mesa, CA.

March 2002- January 2003: Consulting Position, Full Time Contract. Six

Months,Job Title: H/W Test Engineer.

Duties: Full ASIC Validation on Laser Guided Imaging Die, running at two

500MHz internal Clocks. Design Test Fixtures using ORCAD and PCAD for PCB

Design and using Xilinx FPGA for implementing test logics into the test

fixture. Generating test automation using National Instrument PCI DAQ and

Labview 6.1 to test and validate all new Die's using Micro probing

technique and Chip on Board for Vth, Mux, full FIFO and End to End

functional test.

STM Wireless Inc. Irvine CA. November 2001 - Jun 2002. Lay off. Job Title:

Sr. Mfg Test Engineer.

Duties: Support manufacturing floor for all board and system level test

setup and configuration on C-Band, L-Band and Ku-Band satellite modems and

network Hub's. Writing production test / debug procedures, plus test

automation tools using National Instrument Lab View 6.1 for Windows and RF

Switches DC-18GHz. Working closely with H/W design team during design phase

to design test fixtures using ORCAD to validate and debug Digital, Analog

and RF boards for new design, complete DVT test procedures. Extensive

knowledge of RF design, Phase noise, and spurious measurement. Using

Spectrum Analyzer, Power Meter, Signal & RF Generator, BER Tester and Logic

Analyzer. RF Test Equipments Calibration and Rental Scheduling. Supervise

and train all Mfg Technicians. Contract, Full Time Position. Six Months.

DSS Networks Inc. Irvine CA. September 2000 - May 2006. Contract Position,

Job Title: Sr. H/W Design & Validation Engineer. Duties: Schematic Capture,

using ORCAD & McCad for board level design and PCAD for layout. Test

development, Troubleshooting, Debug and Signal Integrity on all new PCI,

PCI-X, PMC and cPCI Gigabit Single/Dual Ports, Including Copper and Fiber

boards up to 8 layers Network Cards using Intel PCI Bridge, National, Intel

and Broadcom Gigabit MAC / PHY plus Marvell, Vittesse or Agilent SERDES.

Complete FCC (Part 15), CE and UL Test certification using third party test

labs. Contract Part time.

Rainbow Technology, Inc. Irvine CA. Sept 1999 - Nov 2001. Job Title: Sr.

H/W Test Engineer. Laid Off

Duties: Working closely with Sr. H/W Design Engineers to develop and

troubleshoot all new PCI, CPCI and PMC Cryptographic SSL accelerator boards

in Linux and Windows NT Platforms using Catalyst PCI Bus Analyzer. Evaluate

test equipments and furniture's to layout Hardware Engineering Lab.

Complete DVT Test Procedures and reports for full characterization and

validation of all new designs. Complete FCC (Part 15), CE and UL Test

reports using third parties test labs. Complete full DVT and Compliance

tests on Cryptographic SSL Network Proxy Accelerator server. Complete

troubleshoot and debugging USB low and full speed iKey Tokens using USB Bus

Analyzer, Tektronix USB Compliance test package. Full DVT and Environmental

test reports, plus Compliance tests on USB ikey modules. Automate DVT Test

procedures using National Instrument Lookout and Labview software

interfacing Fieldpoint Analog I/O, Data Acquisition and Relay modules to

control programmable power supply Test Chamber. Monitor and logging data

for all electrical parameters like In-Rush Current, Voltage Droop and

temperatures data.

Viking Components Inc., Rancho Santa Margarita CA. Nov 1997, Sept 1999. Job

Title: Sr Test Engineer.

Duties: Design SDRAM, PC100, PC133, DDR and Rambus memory modules for PC's

and Servers. Schematic captures and board layout for test fixtures using

ORCAD &ACCELL EDA. Develop test procedure to test all different type of

high-speed memory modules using HP83000 F330I and Advantest Rambus ATE and

GenRad in circuit tester. Develop DVT test procedures on all new memory

modules for signal integrity and AC-DC characterization using Tektronix

TDS694C Oscilloscope and HP 10674, logic analyzer. Troubleshoot and analyze

all field failure returned modules from OEM and write corrective action

reports for all failures and developing new test using ATE testers.

Supervise & Train technicians.

Western Digital Corp. Irvine CA. Sept 1996 To Nov 1997. Job Title: Sr.

Validation Engineer. Laid Off

Duties: Test and Validate R/W Channel Chip for Analog and Digital Blocks.

Design the Test Bed to simulate hardware environment using ICE (In Circuit

Emulator, Intel 8xc196 NU & NP) using NOHAUE Software for mapping memory

Blocks of the Test Bed. Using Altera and Lattice FPGA (7000 & 8000) series

to design logic's and ORCAD tools for schematic capture. Writing and

translating Sims in Verilog and using Visual C++ on UNIX to simulate and

correlate the Sims against Test Bed. Troubleshoot and upgrade the test Bed

according to the latest changes to the R/W Channel chip specification.

Using Arbitrary Waveform Generator, HP and Tektronix Logic Analyzer (16550C

& TLA 700), Lecroy 10G Sampling Scope and Microprobing for Validating the

analog Blocks.

LATTICE CORPORATION, Hillsboro OR. Oct 1994 To Sept 1996. Job Title:

Component Test Engineer. Moved to CA.

Duties: Test and debug devices for characterization and validation of all

GAL, pLSI and PLD parts

Using Credence ATE, Semiconductor Analyzer, Pulse Generator Tek HFS 9003,

Sampling Scope Tek 11801A,

Data Generator HP800A, DC Power Supply and DVM to analyze signals level

for Tpd, Tco, Tsu, Fmax,

Input translator and Glitch. Write test programs for ATE. Collect and

Graph data using MS Word and Excel.

INTEL CORPORATION. Hillsboro OR. May 1992 - Oct 1994, Job Title: Hardware

Engineer Assistant. Contract Long Term.

Duties: Build Prototype Board PCI Card for 486/Pentium base Processor, Fax

/Data and DSVD Telephony internal board. Draw Schematics using ORCAD and

CADANCE, Debug and troubleshoot the Prototype 1and 2, in order to pass FCC

and LU Test. Build test station for Functional test and reliability test.

SMT Soldering and repair the boards for Remote LAN Access network Server

product. Build, Test and configured systems for LAN/WAN network using

network and ISDN Cards. Build Test setup for the server to pass FCC and

EMI Test. Using SPEED, MAX and EXCEL Spreadsheet for BOM and Data

Collections. Contract Job.

Status: US Citizen

REFERENCES: Available upon request.

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