Engineer Design

Jina Shumate

**** *. ******** **. (***) *** – ***0 Mobile: (480) 275 – 9847

Phoenix, AZ 85044 Email: ****.*******@*****.***

Summary of Qualifications:

• 9+ years of managing discrete MOSFET design groups for Low Voltage (LV) and Medium Voltage (MV)

• Several years of technical support for the manufacturing engineering team

• Increased new product sales in computing, portable/consumer and automotive/ general industrial markets

• Demonstrated leadership with a design community to release new products on time

• Experienced in various areas of discrete product design, product data analysis, processing, manufacturing

and meeting the company’s goals (cost reductions, yield improvement and technical customer support)

• Collaborated well with other areas of engineers (product, test/characterization, application, reliability,

packaging and manufacturing) to effectively launch new products to the market

• Obtained technical skills (TCAD and design/layout) and data management skills (Excel and JMP) to

increase productivity and efficiency

• Driven-in multi-tasking, prioritization and the coordination of several projects to meet the objectives

Professional Experience:

ON Semiconductor, Inc. July 2003 – August 2012

Power MOSFET product design engineering manager

• Managed engineers for Low Voltage (LV) and Medium Voltage (MV) MOSFETs design group, which

encompasses.

Involved actively in roadmaps, future technology brainstorming and discussions

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Evaluated the conceptual design against the customer requirements by utilizing existing device

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library or TCAD (process and device) simulation

Created layouts, primitives and schematics of device, including ESD if necessary, utilizing Mentor

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Graphics

Used the design of experiment (DOE) approach to optimize the parameter matrix to achieve the

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targeted goals

Characterized the device designed data

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Benchmarked competitor’s products/ technologies for the next generation of development

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Owned technology platform definitions and executed development activities via performing bench

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characterization of devices, test structures, and process monitor to identify and analyze processing

issues on electrical performance and reliability

Worked with product engineering, application, reliability and packaging teams to ensure quality

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products and resolved any new product related issues.

• Took initiative and ownership in working with internal fabs and foundries to develop and qualify new

products and demonstrated flawless NPI (New Product Introduction) to the market

• Provided technical support to manufacturing, reliability and application teams for a successful product

transfer

Motorola, Inc./ON Semiconductor, Inc. December 1998 – June 2003

Power MOSFET design engineer

• Performed TCAD simulation on cell design of charge balanced trench MOSFET for HV

• Performed TCAD simulation on cell and termination designs of Planar and Trench MOSFETs for LV and

MV

• Performed device design and layout for MV

• Characterized the device data

Motorola, Inc.

GaAs process and device engineer November 1996 – November 1998

Bipolar (BP) 5 process and device engineer December 1992 – October 1996

Material Organization process engineer January 1989 – November 1992

• Monitored device yield for various products and improved products yields by utilizing DOE approach and

TCAD simulation

• Implemented new process spec and worked with manufacturing personnel to ensure that they knew the

spec change and followed it

• Responsible for Photo Lithography and Etching process for many BP devices

• Developed front metal etching process to eliminate pattern recognition issues seen at assembly, which

resulted in improving productivity

• Setup and performed Statistical Process Control (SPC) and Gauge Capability tests on photo and etch tools

for process control which minimized rework

• Worked with many internal front-end fabrication customers to improve front-end device yields or resolve

front-end device issues affected by starting material (Oi, Slips, Bow and Warp, etc.)

• Obtained Computer application skills in Microsoft Office (Words, Excel, Power Point and Project

Management) and JMP

Education:

• Bachelor of Science in Chemical Engineering University of Illinois (Urbana – Champaign)

• Master degree Classes Arizona State University

Introduction to device theory

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Semiconductor device physics

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Device characterization and failure analysis

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Statistics

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Awards Received:

• BP5 Excellence Award, Outstanding achievements in support of BP5’s scrap reduction goals, August, 1995

• Recognition Award of “FET New Product Development with Zero Rework”, October, 2006

• Certificate of Appreciation for the commitment and leadership in introducing Next Generation MOSFET

Computing Portfolio, April, 2008

• Certificate of Appreciation for the commitment in introducing MOSFET + Schottky (FETKY) for Apple,

May, 2009

Publications / Patent:

• “ The Warpage of as-received and Oxygen Precipitated CZ Silicon wafers”, Extended Abstract, Spring

Meeting, The Electrochemical Society, May, 1992

• “Warpage and Oxide Precipitate Distributions in CZ Silicon Wafers”, Journal of the Electrochemical

Society, July, 1994

• “Effect of Substrate Oxygen Content on Leakage of Switching NPN Transistors and Diodes”, The

Electrochemical Society, May, 1995

• “Reduction of Variation in Reflectivity of Al and AlSi Top Metal”, Defensive Publication, August, 1995

• “Effect of Oxygen Content, Backside Damage and Polysilicon Backsealed Substrate on Switching

Transistors and Diodes”, 1996 International Conference on Semiconductor Electronics, November, 1996

• “High Voltage GaAs Rectifiers for Advanced Conditioning Applications”, 13 th Annual Applied Power

Electronics Conference, February, 1998

• U.S. Patent No: 6756273 Date issued: June 29, 2004

Title: Semiconductor Component and Method of Manufacture

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