Roy H. Parker

** ******** *****

Nashua, NH ***62

ab2exs@r.postjobfree.com

C: 603-***-****

H: 603-***-****

DIGITAL DESIGN CORE SKILLS

. Exceptional FPGA Design Skills using standard HDLs such as VHDL,

Verilog, and SystemC as well as Schematic Capture tools on

ASICs/FPGAs/CPLDs

. Sim/Place/Route tools: Modelsim, Xilinx ISE, Active-HDL, Diamond 2.0

. Synopsys- Primetime, Formality, Design Vision, Synplify-Pro, Actel

Designer

. Industry Standard Logic Devices - Xilinx, Altera, Actel, Lattice

including: Virtex-E, Virtex II PRO, Virtex-4, Virtex-5, Kintex7, and

MachXO2

TEAM SKILLS

. Project Engineer for teams of size three to twelve people - Omnify,

Microsoft Project

. Experienced establishing new FPGA designs/products and bringing them

into production

. Continuously chosen for projects for multidisciplinary teams and

offsite teams due to excellent communication skills

. Proven troubleshooting skills for integration teams

PROFESSIONAL EXPERIENCE

Support Chief Technical Staff - FPGA Design - Raytheon, 2013 (Contract)

. Enhanced multiple FPGAs for newest Raytheon SATCOM Product Line Design

o Upgraded an FPGA Interface control for a new external DDS

o Completed a legacy FPGA Design with legacy tools to prevent

redesign of board

FPGA Design Engineer - DRS Technologies, 2012 (Contract)

. High Speed Data Link Block Design Consultant - Design and Instruction

Senior Electrical Engineer - DRS Technologies, 2009 - 2012

. FPGA Design Engineer for Direction Finding, Acquisition,

Communications Products Including Architecture, RTL Design,

Simulation, Synthesis, Place and Route

. Project Engineer for Acquisition Products Including Liason to PM,

Coordinating Product effort among all disciplines, Tracking

deliverables from ordering through assembly to final Inspection,

Running weekly status meetings, Product Obsolescence replacement,

Redline Documents, Waiver Grants, Vendor Communications, Entering

Change Notices into Database, Forecast resources, Review/update BOMs

. Added timestamp capability to existing FPGA design to match current

data flow.

. Created High Speed Data Link block to transfer data in 2 directions

around a ring of FPGAs to ensure every unit could talk to every other

unit using Aurora 8b10b cores

. Updated DSP cores for multichannel signal intercept/analysis design,

updated DDR2

Senior Electrical Engineer II - Raytheon, 2005 - 2009

. FPGA Design Engineer for Receiver/Exciter Department for Radar

Programs Including Architecture, RTL Development, Verification,

Synthesis, Timing Closure

. System on a board Design - Architect and Design Solutions on COTS

boards

. Design of Digital Beam Former complex data sample channel creation

Roy H Parker

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Senior Electrical Engineer II - Raytheon, 2005 - 2009 (Continued)

. Developed Narrow Band Down Converter FPGAs to control Data Flow

. Architected and Inserted an Electromagnetic Interference Notification

capability to existing RADAR system - 5 FPGA solution - no hardware

changes

. Upgraded legacy radar design from 6 boards to one mounted with a CPLD

FPGA Design Engineer - Hamilton - Sundstrand, 2005 (Contract)

. Ownership of Design/Ver. of FPGAs - Engine Control System of Joint

Strike Fighter.

. Dropped into a project in the middle of the schedule to bring closure

to project

. Came up to speed on customer's tools/processes for immediate impact to

meet deadlines

. Identified Test escapes and advised on proper design solution and

verification patch

. Lead Code Reviewer on 9 out of 11 FPGAs in development

ASIC Design Engineer- Seagate Technology, Inc., 2001 - 2004

. Block level RTL Development for Personal Storage Group of Disk

Controllers with 3-6 month cycle time of multi-million gate SOCs

. ASIC Group taped out 8 chips in one calendar year - SATA and PATA

versions

. Responsible for Architecture/Design/Verification, Gate-Level

Simulation, Debug, Place and Route, Design Reviews, Use of 3rd party

logic blocks

o Instruction Tightly Coupled Memory Cache for ARM microprocessor

. First Logic Block integrated into COSIM verification environment with

software group

. Buffer Cache Block for ST Uproc - 12 Line Read only Cache Controller,

Scalable

o Design changed to accommodate larger line limit with NO hit to

design schedule

ASIC Design Engineer- Infineon Technologies, Inc. 1999 - 2001

. Integration of customer's logic with native microcontroller for use in

Disk Drives

o SCAN Insertion - Fault Coverage Analysis - Testbench

Creation/Regression

o Timing Issue Identification and Timing closure - False path

Identification

New Products Development/Memory Test Engineer- Austin Semiconductor, Inc.

1997 -1999

. Facilitation of new products - conception to production -

Custom/Memory Test

o Part types include EEPROM, SRAM, DRAM, FLASH, and UVEPROM

. Consignment Die Verification of Memory for Military specs - program

stalled for 5 years

EDUCATION

MS - Electrical Engineering, University of Colorado at Boulder

Specialty: VLSI Design, 2 DSP classes

BS - Electrical Engineering, University of New Hampshire, Durham, NH

Engineer-in-Training Certificate # 3380

PUBLISHED ARTICLES

Roy H Parker, "Caution: Clock Crossings" Chip Design Magazine, A

Methodology for Crossing Clock Domains, June 2004

Other

Basketball Official- IAABO Certified

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