Design Engineer

Shreyas HS Bharadwaj

*** ********** ** ***-***, Santa Clara CA 95051 210-***-**** *******.*********@*******.***

linkedin.com/in/shreyasbharadwaj

Electronics engineer with a masters degree and focus on mixed-signal circuits. Highly organized and self-motivated with strong lab skills looking for a position in the semiconductor field.

Mixed signal circuit design and layout

Testing (IC and Board level)

Memory design and layout

Semiconductor device fabrication

EDUCATION

Master of Science in Electrical Engineering Aug 2011 – May 2013

Arizona State University, Tempe AZ

Bachelor of Engineering in Medical Electronics Sept 2007 – June 2011

Visvesvaraya Technological University, India

INDUSTRY EXPERIENCE

Intern (Undergrad), Philips Inc. Feb 2011 – Jul 2011

o Developed GUI using C# on visual studio IDE, enabling user to easily retrieve and sort images.

o Suggested ideas for improvement, and implemented it to include data sorting, classification and archival methods.

o Developed and introduced tool which enabled to automate manual sorting, saving more than 50% of work time.

PROJECTS

Research work - Design, Fabrication and Characterization of Low Power Active Feedback System

• Designed a 2-stage amplifier with active feedback and low pass filter for medical applications. Developed custom layout with common centroid and interdigitation. Completed using AMI_C5 (0.5µm technology) process

• Incorporated sub-threshold operation with 10µW total power usage, with 50dB gain and high noise stability

• Characterized the I-V characteristics, power, noise rejection and gain on a custom board setup

Schematic and PCB design of SODIMM Baseboard on Altium

• Carrying out the Schematic and Layout design of PCB for SODIMM baseboard of an Embedded computer

• Project carried out on Altium designer for PCB design. Prepared BOM report, Footprint and 3D models of components

SRAM and Memory Cache Design

• Developed 5kb SRAM with 4-way cache design, using 8T unit cells, and completed layout verification using Mentor Graphics Calibre tool. Addressed problems such as ‘half select’ and completed Monte-Carlo analysis for VT corners

• Developed a 32Kb cache memory with 5kb SRAM, using HSPICE. Project completed using 45nm PDK process

Custom Amplifier Design

• Designed folded-cascode, telescopic-cascode, rail-to-rail and operational transconductance amplifiers

• Specifications include high gain, low input noise, gain margin, phase margin, gain bandwidth product, CMRR, PSRR

• Completed the design and layout using TSMC03 0.25µm process technology

Optimization of Online order to increase sales and throughput of production line

• Improvised the process from order to fulfillment for Online book orders

• Analyzed process on IDEF0 modeling for red flags such as bottlenecks and loopy-loops in the process

• Suggested and implemented improvisations from a managerial viewpoint to decrease cycle time

Design of supply sources for constant Current reference and Voltage reference

• Design of bandgap voltage reference circuit and Constant transconductance current reference.

• Output modelled to be insensitive to supply variations with a power spec of 0.25µW

Automotive Engine Controller IC Design

• IC developed for controlling a 6-speed 12-cylinder engine, with RPM control and auto-pilot mode

• Simulation and layout development completed using Cadence Spectre integrated environment at 0.25µm process

GRADUATE COURSEWORK

Advanced Analog Integrated Circuits, Advanced VLSI Design, Semiconductor Device Theory, Analog Integrated Circuits, Low-Power Bio Electronic Circuits, Digital Systems, VLSI Design, Digital Signal Processing, CMOS and MEMS Fabrication Techniques

TECHNICAL TOOLS

Programming & Scripting Tools: C#, C, C++, Perl, SPICE, Assembly level

EDA Tools: Cadence Virtuoso, Mentor Graphics Calibre, Altium

HDL Tools: VHDL, Verilog

Simulation & Modeling Tools: Cadence Spectre, HSPICE, MATLAB, ModelSim, COMSOL

HONORS

o Placed in the top 2% in SAT Exam, completed undergraduate degree with scholarship

o Served as president of the student technical council during senior year

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