Electrical Engineer

Divya Pratap

Apt#*** ,**** E Lemon Street, Email:*******@***.***

Tempe, AZ 85281- USA Contact:480-***-****

Objective: To be part of a team where I can make valuable contributions and continue learning in my area of interest.

Summary: A highly motivated and goal oriented individual Experienced with writing Scripts for verification and designing circuits for low power performance. I work well on my own but always contribute to the team as a whole.

Professional Experience:

Microsystems Development Engineer Intern Jan08-Dec08

Sensor & Actuators (MEMS-MST) Division, Freescale Semiconductors, Tempe, AZ-USA

Projects:

Mercury Matlab Model

o The MERCURY device is a 3axis low g (1g-6g)- MEMS-accelerometer device.

o Developed a Matlab Stimuli model that has a Stimulus section, a Sensor section and an ASIC section.

o The Stimulus section allows text file, sinusoidal, square wave, or constant acceleration input to the Sensor section.

o The Sensor section is a three mass damper spring system representing the mechanics of the package, die attach and the g-cell.

o The output of the Sensor section is a capacitance value that is feed into the ASIC section.

o The ASIC section behaves as an ideal signal path with the same timing as the ASIC CMOS design - CtoV, 2nd stage gain, 3rd stage trim gain, 400 Hz filter, and the output gain. The model was adjusted to emulate typical production devices.

Bcrux –gCell Model

o Designed the Verilog-AMS model for the gravity cell which is the part of the transducer section of accelerometer.

o Responsible for MEMS level testing and verification for full chip sensor IC’s.

o Written the Verilog-AMS scripts for Validation / Verification of the full chip.

o Worked with the R&D group in developing the algorithm to minimize offsets produced by temperature variation.

o Develop the trimming code for compensation of temperature dependence of linearity and sensitivity.

Tron Medium-G Accelerometer

o Perform the Noise Analysis for the ASIC & Gcell. Thus Developed the Noise model stating the effects of noise on sensitivity.

o Lead a team of two people to study the rotation effects on the sensitivity of all three axes.

o Designed the model compensating the rotation effect and thus help in increasing the Tilt motion sensitivity.

o Helped the MEMS designer to study the effect of ASIC timing in the resonance frequency of Gcell.

Research Experience:

 Graduate Assistant , Arizona State University ,Tempe Aug07-Jan08

o Developed the research proposal for the design of Micro machined (MEMS) Cyclotron.

o Designed interface circuit schematics, making device to work on 1.8V power supply under 1T magnetic field at near 2 GHz.

o Performed simulation for FEM analysis in ANSYS and COVENTOR environment for electro magnetic characterization.

o Developed the layout for full device in Cadence and VirtuosoXL.

o Professional document discussing the fabrication and process steps used was drafted for NPI entry in Sandia.N.Labs.

o Micro machined Cyclotron was the first attempt ever tried by anyone.

 Independent Research Study , Arizona State University-Freescale Semiconductor , Tempe Oct08-Dec08

o Design a VLSI Phase-Locked Loop circuit for data recovery for a 1.6Gb/s high-speed I/O circuits.

o Design Specs: Input reference clock frequency-100MHz , Output clock frequency 1.6Ghz (equally spaced 4-phase clocks) 1.8-Volts supply, 0.18um TSMC CMOS process technology.

o Design a 4-phase replica-biasing Ring Oscillator VCO .

o Design Specs: Power supply: Vcc = 1.8V+/- 10%, Minimal frequency tuning range (typical/27C):1G- 3.5Ghz.

o Simulated the designed for DJ content (RMS and pk-pk of absolute jitter) with a 20mV pk-pk noise of 50Mhz added to Vcc.

o Developed the Scripts in Verilog-HDL for compensating the process corner frequency variation.

o I have written the Algorithm the controllers, shifters and adders.

o Architect the Control model system for process corner frequency variation.

o Developed the Full control circuit Model using SystemC & HDL.

Academic Projects:

 Performance Analysis of Cache Controller: Oct08-Dec08

o Designed the code for obtaining numbers showing the dependency of access time on Cache Associativity, RAM size.

o Performed the experiment run on Design-Expert thus concluding the dependency of interaction of all factors.

 Designed a Telescopic Cascode amplifier: Jan08–Mar08

o Designed Differential Stage with wide swing both at schematic and layout level.

o Design Specs: DC gain 50dB, Unity Gain Frequency-70MHz, Common centroid approach for layout design.

 Design a single ended PMOS input Folded Cascode Amplifier: Jan08–Mar08

o Designed the amplifier with a Class AB Output Buffer Circuit to drive a 50 ohm amplifier.

o Design Specs: PSRR: 55dB at 10 kHz, Input referred noise-10nV/sqHz.,Slew rate-10V/u-sec,HD3-50dB, with 1V differential peak-to-peak swing driving differential 1kohm resistance.

 Issue Queue Logic for Out of Order Microprocessor: Jan08–Mar08

o Designed a 32 entry Instruction queue with 64 Physical Registers taking 4 instructions per clock cycle.

o Used CAM cell in maintaining status of physical registers for source operands.

o Designed in order to reduce the power and speed up the Processor by targeting WakeUp & Selective logic.

 Design of SRAM Array: Aug07-Dec07

o Designed a 4KB SRAM Array using 6T-cell.

o SRAM Array and control circuits Layout was drawn and extracted for simulation.

 Design of 32 bit ALU: Aug07-Dec07

o Designed an adder with Carry Select Architecture using power efficient ADD ONE algorithm

o 32 bits FlipFlop Array and control circuits-Shifter& Adder Layout was drawn and extracted for simulation.

Education

 Master of Science in Electrical Engineering , Arizona State University , Tempe , USA Aug07-Dec08

o Relevant Coursework- Advance VLSI, High Speed I/O circuits, Advance Analog Circuit Design, MEMS Electronics Design of Experiments, MEMS Process and Fabrication, Computer Networks.

 Bachelor of Technology in Electrical And Electronics Engineering , UPTU, India Aug03-May 07

o Relevant Coursework- Switching Circuits Logic Design, Microelectronics, Microprocessors, Adv. Control systems.

Skills/Tools:

HDLs: SystemC, VHDL, VERILOG-A, Verilog-HDL.

Software Languages: C, C++, Assembly language, Perl, MatLab, HTML

Operating System: Windows 9X, NT, ME, 2000, XP, MS- DOS, Linux

Application Software: Design-Experts,LabView, Solid Works, Ansys, Coventer , MS Office XP (Word, Power Point, Excel)

Simulation: Modelsim SE6.0a, Cadence NC-VHDL / NC-Verilog, HSPICE , Simulink, Spectre, Discover

Debug tools: Trace-2, Signal Tap- Logic Analyzer,

Achievements & Co-Curricular Activities:

 Event co-coordinator for Travel and Tourism organization ,Arizona State University, Tempe ,US Aug’07-Dec’08

 Mega Personality scholarship for consistent performance by Krishna charitable society. Jan’04-March’07

 Volunteer, Smriti Social Organization, helped and encouraged youth in quitting smoking. Feb’03- Dec’06

 Presented paper on Silicon Cantilever Biosensor to detect Biomolecules ,Ghaziabad ,India Nov’2006

 Best lead actor award in a play ‘ Samaj kalian ’ , by Regional Arts Society , Uttaranchal , India. Dec’02

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