| Resume alert | Resumes 31 - 40 of 318 |
Telugu Engineering
Hyderabad, Telangana, India
... KEY SKILLS: MATLAB Hands-on experience in VLSI Basics of java Ms word,excel,PowerPoint C language EXPERIENCE: Two years experience in private school office work. CO-CURRICULAR ACTIVITIES: In dipoma successfully completed my 6 months training in ... - 2021 May 02
... KEY SKILLS: MATLAB Hands-on experience in VLSI Basics of java Ms word,excel,PowerPoint C language EXPERIENCE: Two years experience in private school office work. CO-CURRICULAR ACTIVITIES: In dipoma successfully completed my 6 months training in ... - 2021 May 02
Engineering Engineer
Hyderabad, Telangana, India
... E CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY OU HYDERABAD 2020 · Branch: Embedded systems and VLSI design · CGPA: 8.0 (pursing) B. TECH BVRIT HYDERABAD COLLEGE OF ENGINEERING FOR WOMEN JNTU HYDERABAD 2018 · Branch: Electronics and Communication ... - 2021 Mar 19
... E CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY OU HYDERABAD 2020 · Branch: Embedded systems and VLSI design · CGPA: 8.0 (pursing) B. TECH BVRIT HYDERABAD COLLEGE OF ENGINEERING FOR WOMEN JNTU HYDERABAD 2018 · Branch: Electronics and Communication ... - 2021 Mar 19
Engineering Sales
Hyderabad, Telangana, India
... Education 2016 Full time 81 10th Cyber Age Pupills High School Board of Secondary Education 2014 Full time 7.8 SKILLS:- Basics of MATLAB software & VLSI MS-Office& MS- Excel EXPERIENCE:- Had an internship for 1month at NSIC on embedded systems. ... - 2021 Mar 15
... Education 2016 Full time 81 10th Cyber Age Pupills High School Board of Secondary Education 2014 Full time 7.8 SKILLS:- Basics of MATLAB software & VLSI MS-Office& MS- Excel EXPERIENCE:- Had an internship for 1month at NSIC on embedded systems. ... - 2021 Mar 15
Engineering Project
Hyderabad, Telangana, India
... track Assembly and Disassembly Workshop related to mechanical engineering conducted by Ezenith Education Participated in VLSI workshop held by IETE-ISF VBIT Participated in IOT workshop held by Robotics club Date of Birth:09/11/1998 Place: Hyderabad - 2021 Mar 14
... track Assembly and Disassembly Workshop related to mechanical engineering conducted by Ezenith Education Participated in VLSI workshop held by IETE-ISF VBIT Participated in IOT workshop held by Robotics club Date of Birth:09/11/1998 Place: Hyderabad - 2021 Mar 14
Engineering Design
Hyderabad, Telangana, India
... Educational Qualifications: QUALIFICATI ON INSTITUTION BOARD YEAR OF PASS OUT PERCENTAGE M Tech (VLSI DESIGN) BHARAT INSTISTUTE OF ENGINEERING AND TECHNOLOGY JNTUH 2018-2020 71 B-Tech (ECE) GURUNANAK INSTISTUTE OF TECHNICAL CAMPUS JNTUH 2014-2018 67 ... - 2021 Mar 11
... Educational Qualifications: QUALIFICATI ON INSTITUTION BOARD YEAR OF PASS OUT PERCENTAGE M Tech (VLSI DESIGN) BHARAT INSTISTUTE OF ENGINEERING AND TECHNOLOGY JNTUH 2018-2020 71 B-Tech (ECE) GURUNANAK INSTISTUTE OF TECHNICAL CAMPUS JNTUH 2014-2018 67 ... - 2021 Mar 11
Office Power
Hyderabad, Telangana, India
... ● Participated in webinar on VLSI methodologies and member of IETE. PROJECT HANDLED Major Project: RFID Connection and RFID Technology for Sensing the Internet of Things Description: Everything must be connected, monitored and networked this is the ... - 2021 Feb 23
... ● Participated in webinar on VLSI methodologies and member of IETE. PROJECT HANDLED Major Project: RFID Connection and RFID Technology for Sensing the Internet of Things Description: Everything must be connected, monitored and networked this is the ... - 2021 Feb 23
Design Engineer Power
Hyderabad, Telangana, India
... Kannada tech Layout Designer(2018-2019) The internship held in campus of RNSIT for 6 months The vlsi cad is introduced,basic layouts different ways of making layouts has be observed and created basic cells. The project of making standard cell ... - 2021 Feb 19
... Kannada tech Layout Designer(2018-2019) The internship held in campus of RNSIT for 6 months The vlsi cad is introduced,basic layouts different ways of making layouts has be observed and created basic cells. The project of making standard cell ... - 2021 Feb 19
Assistant Engineering
Hyderabad, Telangana, India
... Tech – VLSI Systems Design Completed in November, 2012 with 71.14 % passed in First Class with Distinction. JNTUK 2010 India B. Tech - Electronics and Communication Engineering Completed in May, 2010 with 66.55 % passed in First Class. BOARD OF ... - 2021 Feb 14
... Tech – VLSI Systems Design Completed in November, 2012 with 71.14 % passed in First Class with Distinction. JNTUK 2010 India B. Tech - Electronics and Communication Engineering Completed in May, 2010 with 66.55 % passed in First Class. BOARD OF ... - 2021 Feb 14
Design Verification Intern
Hyderabad, Telangana, India
... (Track1 & Track2) from ISRO ● Certificate of Participation in The Future of web policing and cyber opportunities ● Certificate of Participation in webinar on Formal Verification: Significance in VLSI Design Flow & SystemVerilog Assertions(SVA). ... - 2021 Feb 12
... (Track1 & Track2) from ISRO ● Certificate of Participation in The Future of web policing and cyber opportunities ● Certificate of Participation in webinar on Formal Verification: Significance in VLSI Design Flow & SystemVerilog Assertions(SVA). ... - 2021 Feb 12
Software Developer/Engineer
Hyderabad, Telangana, India
... – Sir CRR Polytechnic Eluru with 76.2 High School (2012) (S.S.C) – SSPL ZPHS Gollaprolu with 8.2 GPA ACHIEVEMENTS Certificate in Workshop/Seminar/Conference titled VLSI - FPGA Programming held at PYDAH College of Engineering on 27th-28th July 2018. ... - 2021 Feb 11
... – Sir CRR Polytechnic Eluru with 76.2 High School (2012) (S.S.C) – SSPL ZPHS Gollaprolu with 8.2 GPA ACHIEVEMENTS Certificate in Workshop/Seminar/Conference titled VLSI - FPGA Programming held at PYDAH College of Engineering on 27th-28th July 2018. ... - 2021 Feb 11