| Distance: | Resume alert | Resumes 41 - 50 of 821 |
Electronics and communication
Vasant Nagar, Karnataka, India
PALAK Fresher • C • C++ • Multisim Software • Keil Software • MS-Office • Arduino • Basic of PCB design • Basic of VLSI & VHDL • Basic of microcontroller • Circuit design T ECHNICAL SKILLS: • Listening Skills • Team Management • Multi-Tasking • ... - 2021 Apr 16
PALAK Fresher • C • C++ • Multisim Software • Keil Software • MS-Office • Arduino • Basic of PCB design • Basic of VLSI & VHDL • Basic of microcontroller • Circuit design T ECHNICAL SKILLS: • Listening Skills • Team Management • Multi-Tasking • ... - 2021 Apr 16
School Es
Vasant Nagar, Karnataka, India
... (tk) Thir uvanamalai di stri ct Basi csofpcbdesi gn tamil nadu-604601 Basi csofVer il og( VLSI ) Per sonal Dat a: Oper ati ngSy stems: WindowsXP/ 7 Dat eOfBi rt h :24/ 05/ 1999 Of fi ceAut omat ion: MS- Off ice: Wor d,Excel ,andPower Poi nt. ... - 2021 Apr 07
... (tk) Thir uvanamalai di stri ct Basi csofpcbdesi gn tamil nadu-604601 Basi csofVer il og( VLSI ) Per sonal Dat a: Oper ati ngSy stems: WindowsXP/ 7 Dat eOfBi rt h :24/ 05/ 1999 Of fi ceAut omat ion: MS- Off ice: Wor d,Excel ,andPower Poi nt. ... - 2021 Apr 07
Security Engineering
Vasant Nagar, Karnataka, India
... Achievement • Attended workshop of ‘VLSI’ held at BANGALORE. Education Aug 2016 - Sep 2020 Maharaja Institute of Technology Thandavapura Bachelor of Engineering (Electronics and communication Engineering) CGPA : 7.18 Jul 2014 - Apr 2016 Government ... - 2021 Apr 01
... Achievement • Attended workshop of ‘VLSI’ held at BANGALORE. Education Aug 2016 - Sep 2020 Maharaja Institute of Technology Thandavapura Bachelor of Engineering (Electronics and communication Engineering) CGPA : 7.18 Jul 2014 - Apr 2016 Government ... - 2021 Apr 01
Engineer Java
Bangalore, Karnataka, India
... Attended the webinar on VLSI in Maven silicon and perceived the certificate from Maven silicon. I participated as a volunteer in “KALPAYANA (ISRO Exhibition)” Personal Details: Name: Ranjana K R Father’s Name: Ramesh M Mother’s Name: Sujatha K R ... - 2021 Mar 21
... Attended the webinar on VLSI in Maven silicon and perceived the certificate from Maven silicon. I participated as a volunteer in “KALPAYANA (ISRO Exhibition)” Personal Details: Name: Ranjana K R Father’s Name: Ramesh M Mother’s Name: Sujatha K R ... - 2021 Mar 21
Information C
Vasant Nagar, Karnataka, India
... Completed my Internship on VLSI using Cadence Tool. Participated in e-Yantra Robotics Competition(eYRC 2019-20) and got a Certificate of Completion Successfully modeled an Obstacle avoiding car using Arduino. Design of 8-BIT VEDIC MULTIPLIEER using ... - 2021 Mar 21
... Completed my Internship on VLSI using Cadence Tool. Participated in e-Yantra Robotics Competition(eYRC 2019-20) and got a Certificate of Completion Successfully modeled an Obstacle avoiding car using Arduino. Design of 8-BIT VEDIC MULTIPLIEER using ... - 2021 Mar 21
Software Developer
BTM Layout Stage 1, Karnataka, India
... Tech (ECE) Vaagdevi Institute of Technology and Science 2020 69.17 Diploma (ECE) Govt.polytechinc college of proddatur 2017 69.15 SSC ZPGHS 2014 8.7 Project: Title: Reversible logic gates and its performances •Heat is an important issue in VLSI ... - 2021 Mar 16
... Tech (ECE) Vaagdevi Institute of Technology and Science 2020 69.17 Diploma (ECE) Govt.polytechinc college of proddatur 2017 69.15 SSC ZPGHS 2014 8.7 Project: Title: Reversible logic gates and its performances •Heat is an important issue in VLSI ... - 2021 Mar 16
C, C++, basic Python, embedded C, Linux internals, TCP/IP, UART, I2C
Vasant Nagar, Karnataka, India
... • VLSI design using Verilog. • PLC Automation. • Two weeks course on PCB Designing. • Winner in volleyball intercollege match 2015-2016. • Runner up in basketball intercollege match 2018-2019. • DOB :- 17th Aug. 1997. • Marital Status : Unmarried. • ... - 2021 Mar 15
... • VLSI design using Verilog. • PLC Automation. • Two weeks course on PCB Designing. • Winner in volleyball intercollege match 2015-2016. • Runner up in basketball intercollege match 2018-2019. • DOB :- 17th Aug. 1997. • Marital Status : Unmarried. • ... - 2021 Mar 15
Python, Java, embedded c, VLSI, pcb design, IoT
Vasant Nagar, Karnataka, India
GDaivik #*,***'sresidency *ndBcross,pragathinagar hosaroadjunction,Electroniccity,560100 901-***-****,855******* *************@*****.*** CAREEROBJECTIVE Toworkinareputedcompanythathasgoodgrowthprospectandthatmakesthebestuseofmyability,knowledge... - 2021 Mar 09
GDaivik #*,***'sresidency *ndBcross,pragathinagar hosaroadjunction,Electroniccity,560100 901-***-****,855******* *************@*****.*** CAREEROBJECTIVE Toworkinareputedcompanythathasgoodgrowthprospectandthatmakesthebestuseofmyability,knowledge... - 2021 Mar 09
Electrical Engineer Sec School
Vasant Nagar, Karnataka, India
... Co-Curricular Activities Workshops : Virtual Reality, VLSI Design and Applications Seminars : Flexible Electronics Webinars : Artificial Intelligence Achievements Leadership Dutiful Avocations: Photography First position in Oratorical First position ... - 2021 Mar 01
... Co-Curricular Activities Workshops : Virtual Reality, VLSI Design and Applications Seminars : Flexible Electronics Webinars : Artificial Intelligence Achievements Leadership Dutiful Avocations: Photography First position in Oratorical First position ... - 2021 Mar 01
Engineering Engineer
Vasant Nagar, Karnataka, India
... 93% References DR.I.SHIEK ARAFAT,H.O.D,DEPT OF ECE,MOHAMED SATHAK ENGINEERING COLLEGE,KILAKARAI ,RAMANATHAPURAM - Core Competencies EMBEDDED SYSTEM KNOWLEDGE OF SEMICONDUCTOR/VLSI DESIGN,CHIP DESIGN COMMUNICATION ENGG DIGITAL IMAGE PROCESSING - 2021 Mar 01
... 93% References DR.I.SHIEK ARAFAT,H.O.D,DEPT OF ECE,MOHAMED SATHAK ENGINEERING COLLEGE,KILAKARAI ,RAMANATHAPURAM - Core Competencies EMBEDDED SYSTEM KNOWLEDGE OF SEMICONDUCTOR/VLSI DESIGN,CHIP DESIGN COMMUNICATION ENGG DIGITAL IMAGE PROCESSING - 2021 Mar 01