| Job alert | Jobs 1 - 10 of 143 |
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Design Verification Engineer
Intelliswift Software
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San Jose, CA
Design Verification Engineer - Remote / San Jose, CA Duration – 6 months + (can be extended longer) San Jose, CA / Remote Design Verification Engineer UVM System Verilog Test Bench Development SystemC (preferred) strong C/C++ - Apr 26
Senior ASIC Design Engineer
USA Tech Recruitment
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San Jose, CA
... Qualifications: 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V ... - Apr 25
SoC Integration Engineer - Onsite
Experis
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San Jose, CA
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 02
Sr. ASIC Design Engineer
ScaleFlux
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San Jose, CA
... Electrical Engineering or Computer Engineering with industry experience Proven experience of Verilog, System Verilog and C programming Knowledge of DSP algorithm including AES, Hash, ECC codec, data compression is a big plus Knowledge of Embedded ... - Apr 21
Hardware Design Engineer
Sedaa Corp
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San Jose, CA
... Desired Qualifications: Verilog Perl Scripting CAD Tools Job title - Lab Hardware Engineer (Lab Work) Location - San Jose (onsite) The position involves candidate working in Client's Lab, participation and contribution in all phases of hardware ... - Apr 30
SoC Integration Engineer - Onsite
Experis
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Sunnyvale, CA, 94088
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 01
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Design Verification Engineer
Synapse Design Inc.
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San Jose, CA
... Experience:: +10 years Requirements: Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, Perl/Python. Proficient in debugging complex SOC or CPU core designs involving multithreading, scheduling. Experience in triaging ... - Apr 28
Design Verification Engineer
Intelliswift Software
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San Jose, CA
... Pay Rate: $75 to $80/hr Job Description: Testbench development - System Verilog UVM and C tests Integration/development of C tests/APIs and SW build flow Integration/development of UVM mailboxes and HW/SW communication components Test plan ... - Apr 20