| Job alert | Jobs 1 - 10 of 14 |
FPGA Design Prototyping Lead
Mirafra Technologies
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Noida, Uttar Pradesh, India
... - Good understanding of Virtex-7, Virtex Ultrascale and Virtex Ultrascale+ Architectures - Proficiency with Verilog/System Verilog/VHDL and working knowledge of C/C++- Experience in using validation environment test equipment e.g. Logic Analyzers, ... - Sep 23
Senior Design Verification Engineer NOIDA
Renesas Electronics
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Noida, Uttar Pradesh, India
... Good knowledge of Verilog, System Verilog, C/C++, and Shell. Good knowledge in scripting like Perl, TCL, or Python is a plus Proficiency in Metric Driven Verification concepts, and functional and code coverage. Expertise in directed and constrained ... - Sep 23
LLM Hardware Design Developers
Easy Recruit Global
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India Gate, Delhi, 110011, India
... Expertise in HDLs such as Verilog, System Verilog, VHDL, and SystemC. Expertise in scripting, front-end and verification workflows, and integrations within the hardware design environment. Exceptional problem-solving, communication, and ... - Sep 16
Embedded Firmware Engineer
Spraxa Solutions Pvt Ltd
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Noida, Uttar Pradesh, India
... (Nice to Have): Experience with NRF and ESP32 Family Knowledge of GSM modules, RTOS, and SDKs Familiarity with FPGA development (VHDL/Verilog) Experience with ARM Cortex-M microcontrollers and wireless protocols (Bluetooth, Wi-Fi,Ble) Why Join Us? ... - Sep 23
SoC Verification Engineer, Staff
Synopsys Inc
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Noida, Uttar Pradesh, India
... Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant ... - Sep 23
R&D Engineering, Principal Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... Proficiency in HDL languages such as System Verilog and Verilog. Familiarity with digital design concepts and verification methodologies. Experience with scripting languages like Perl or TCL is a plus. Knowledge of protocols such as PCIE, CXL, UCIE ... - Sep 06
Lead Verification Engineer
Cadence
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Noida, Uttar Pradesh, India
... Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage. We’re doing work that matters. ... - Sep 19
R&D Engineering, Sr Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
Requisition Number 51935BR Job Description and Requirements Experience : 7yrs to 12 years Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & ... - Aug 26
ASIC Digital Design, Staff Engineer
Synopsys
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Sector 25A, Uttar Pradesh, 201301, India
... May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Identify design problems, ... - Sep 02
ASIC Digital Design Engineer
Synopsys Inc
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Noida, Uttar Pradesh, India
... flow with experience on industry standard development and verification tools and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Scripting and ... - Sep 23