| Resume alert | Resumes 31 - 40 of 243 |
Iam Jyothi.looking forward for hearing from you
Hyderabad, Telangana, India
... Jeevadan High School Secondary Board of Education-Andhra pradesh 2013 8.8 GPA SOFTWARE / TECHNICAL SKILLS •Language - Beginner C and Verilog HDL •Design tools - MATLAB and Xilinx ISE •MS Office documentation and presentation skills PROJECTS No. ... - 2021 Jan 26
... Jeevadan High School Secondary Board of Education-Andhra pradesh 2013 8.8 GPA SOFTWARE / TECHNICAL SKILLS •Language - Beginner C and Verilog HDL •Design tools - MATLAB and Xilinx ISE •MS Office documentation and presentation skills PROJECTS No. ... - 2021 Jan 26
Engineer Design
Hyderabad, Telangana, India
... Tech] The project is Designing an asynchronous 8-bit up-down counter by using HDL language Verilog. When the strobe bit is at logic 1, It starts up counting else down counting. Design has been verified by using System Verilog. Jan,2014 –April 2014. ... - 2021 Jan 16
... Tech] The project is Designing an asynchronous 8-bit up-down counter by using HDL language Verilog. When the strobe bit is at logic 1, It starts up counting else down counting. Design has been verified by using System Verilog. Jan,2014 –April 2014. ... - 2021 Jan 16
Project Engineering
Hyderabad, Telangana, India
... technical SKILLS: Programming Languages: Intermediate C Language, Embedded C, Assembly Languages, python, Basic Java Script, Basic HTML, HDL (Verilog, VHDL). Knowledge of Microcontroller and Microprocessor: 8051 Microcontroller, AVR ATmega16, PIC ... - 2020 Dec 15
... technical SKILLS: Programming Languages: Intermediate C Language, Embedded C, Assembly Languages, python, Basic Java Script, Basic HTML, HDL (Verilog, VHDL). Knowledge of Microcontroller and Microprocessor: 8051 Microcontroller, AVR ATmega16, PIC ... - 2020 Dec 15
Engineering Design
Hyderabad, Telangana, India
... EDA Tool : Mentor Graphics-Questasim and Xlinix-ISE Domain : ASIC/FPGA front-end Design and Verification Programming Languages : C [Data types Array Pointers] HDL : Verilog Projects Alarm clock project - RTL design:- HDL:- Verilog-2001 EDA Tools: ... - 2020 Dec 10
... EDA Tool : Mentor Graphics-Questasim and Xlinix-ISE Domain : ASIC/FPGA front-end Design and Verification Programming Languages : C [Data types Array Pointers] HDL : Verilog Projects Alarm clock project - RTL design:- HDL:- Verilog-2001 EDA Tools: ... - 2020 Dec 10
Electronics Engineer
Hyderabad, Telangana, India
... Electronics Engineering WORK EXPERIENCE FPGA Intern Sion Semiconductor 06/2020 - Present, Hyderabad VLSI Startup Verilog codes with Testbench for different Sequential and combinational circuits like RealTime Clock, Traffic Light Controler, SPI ... - 2020 Dec 09
... Electronics Engineering WORK EXPERIENCE FPGA Intern Sion Semiconductor 06/2020 - Present, Hyderabad VLSI Startup Verilog codes with Testbench for different Sequential and combinational circuits like RealTime Clock, Traffic Light Controler, SPI ... - 2020 Dec 09
Trainee
Hyderabad, Telangana, India
... TECHNICAL SKILLS: C, SQL, Circuit design, VHDL, Verilog, PCB fabrication, Arduino, IoT, Cadence, Xilinx, Tableau, Qlikview. POSITIONS OF RESPONSIBILITY Member of club Living out loud 2017 Member of club Electech 2018 EXTRA CURRICULAR ACTIVITIES ... - 2020 Dec 09
... TECHNICAL SKILLS: C, SQL, Circuit design, VHDL, Verilog, PCB fabrication, Arduino, IoT, Cadence, Xilinx, Tableau, Qlikview. POSITIONS OF RESPONSIBILITY Member of club Living out loud 2017 Member of club Electech 2018 EXTRA CURRICULAR ACTIVITIES ... - 2020 Dec 09
Engineering Python
Hyderabad, Telangana, India
... SKILLS Languages: C, JAVA,Verilog,Python Softwares: •Matlab. •Simulink •Synopsys •Xilinx-ISE P PROJECTS FPGA Implementation of Dynamic Key Generation Technologies/Languages: HDL Key generation is the process of generating keys in cryptography. A key ... - 2020 Dec 07
... SKILLS Languages: C, JAVA,Verilog,Python Softwares: •Matlab. •Simulink •Synopsys •Xilinx-ISE P PROJECTS FPGA Implementation of Dynamic Key Generation Technologies/Languages: HDL Key generation is the process of generating keys in cryptography. A key ... - 2020 Dec 07
btech in ece from NIT ANDHRA PRADESH
Hyderabad, Telangana, India
... Professional Skills Programming: - C++,Java(basics),verilog. Industry: - Matlab, Cadence, MS-Office. Co-Curricular Activities Conducting and participation in branch association events. Attended workshop on IOT at NIT Andhra. Participation in IOT ... - 2020 Dec 04
... Professional Skills Programming: - C++,Java(basics),verilog. Industry: - Matlab, Cadence, MS-Office. Co-Curricular Activities Conducting and participation in branch association events. Attended workshop on IOT at NIT Andhra. Participation in IOT ... - 2020 Dec 04
Engineering Electrical
Hyderabad, Telangana, India
... TECHNICAL SKILLS MATLAB, LabVIEW, Mi-Power, DSP, Fuzzy, FPGA, Verilog, Proteus, Keil C, C++, Java - 2020 Dec 04
... TECHNICAL SKILLS MATLAB, LabVIEW, Mi-Power, DSP, Fuzzy, FPGA, Verilog, Proteus, Keil C, C++, Java - 2020 Dec 04
Engineering Education
Hyderabad, Telangana, India
... JNTU-K Status Completed, September-2020 Degree Bachelor of Technology - ECE Marks 75% ENGINEERING/TECHNOLOGY Language’s Verilog Module, VHDL Other’s MS-Office/Power Point/Excel ACADEMIC PROJECT Name DESIGN AND ANALYSIS OF APPROXIMATE COMPRESSOR ... - 2020 Nov 26
... JNTU-K Status Completed, September-2020 Degree Bachelor of Technology - ECE Marks 75% ENGINEERING/TECHNOLOGY Language’s Verilog Module, VHDL Other’s MS-Office/Power Point/Excel ACADEMIC PROJECT Name DESIGN AND ANALYSIS OF APPROXIMATE COMPRESSOR ... - 2020 Nov 26