... MATLAB, Simulink, System Verilog) • Lead multidisciplinary design teams, providing clear and effective communication to the team and project manager. • Participate in technical project planning and provide technical inputs to business development ... - Jul 30
... Minimum Qualifications PhD degree with 6+ years or MS with 10+ years of industry experience in digital and mixed-signal design Experience working with machine-learning architectures Experienced with Verilog or SystemVerilog RTL design Experience ... - Aug 05
... Good knowledge of Verilog/VHDL. Experience in C/C++ and interpretive language such as Perl/Python. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without ... - Aug 04
... or processor design experience Strong track record of ASIC/FPGA design from concept to mass production Hands on experience in Verilog HDL coding and verification Experience of high performance ASIC/FPGA design from specification to system bring up ... - Aug 04
... Develop Verilog RTL and assist in building Synopsys HAPS prototyping platforms. Perform electrical and logic validation of DDR/HBM subsystems. Develop C/C++ test platforms and Python scripts for test vector generation. Collaborate closely with ... - Jul 14
... Strong knowledge of Verilog or VHDL, C. Capable of scripting and leveraging automation. Able to set up and maintain automated regressions. Ability to understand design specifications and map them to a test plan. Ability to implement test plans. ... - Aug 04
... Job Responsibilities: Develop formal verification setup using System Verilog modules and Assertions Run formal verification checks, analyze the results, and debug any issues. Develop and enhance constraints, checks, and cover points to achieve ... - Jul 31
... What You'll Do Architect and implement system-level digital signal processing and control solutions using HDL (Verilog, VHDL, or similar). Lead design decisions from initial requirements through to system integration and validation. Collaborate with ... - Aug 05
... Preferred Qualifications Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog. Good fundamental knowledge of front-end tools and methodologies (Verilog simulators, linters, clock-domain crossing, reset domain crossing, ... - Jul 17