| Job alert | Jobs 31 - 40 of 109 |
R&D Engineering, Sr Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Familiarity with Verilog and VHDL HDL/RTL languages. Preferred Experience . Working knowledge of FPGA prototyping tools and flows is a plus. Full time - Apr 13
FPGA Engineer
Paradigm Tech
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VasanthaNagar, Karnataka, 560001, India
... Some networking experience beneficial Experience of working on large Altera and Xilinx FPGA's Knowledge of writing RTL in VHDL Verilog/System or Verilog. In-depth knowledge of Vivado and Questasim. Experience of scripting tools beneficial Please do ... - May 02
Functional Verification Engineer
IBM
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Bengaluru, Karnataka, India
... Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level ... - May 06
Functional Verification Engineer
IBM
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Bengaluru, Karnataka, India
... etc Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience ... - May 06
Lead Solutions Engineer
Cadence
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VasanthaNagar, Karnataka, 560001, India
... Good knowledge of verilog/vhdl/C/C++/Perl/Python. Expertise in AMBA protocols. (AXI/AHB/APB). Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols Good handle on using one or more version control software Good ... - May 05
R&D Engineering, Sr Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis. Working knowledge of FPGA design tools and flows is a plus. Full time - Apr 13
ASIC PDK Development Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
... Should have good understanding of Verilog/VHDL. Exposure to low power techniques and PPA analysis. Knowledge of tcl and perl scripting is a must. Strong presentation and communication skills within an international environment. Team oriented in ... - Apr 08
R&D Engineering, Sr Engineer
Synopsys
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Sadduguntepalya, Karnataka, 560029, India
... Knowledge on Verilog, VHDL or other HDL languages would be plus. Business Title (Title for Job Posting) Senior Research and Development Engineer Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee - Apr 08
Logic Design Engineer, Silicon, Google Cloud
Google Inc
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VasanthaNagar, Karnataka, 560001, India
... 4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in SoC cycles. Preferred qualifications: ... - Apr 13
R&D Engineering, Staff Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis. Working knowledge of FPGA design tools and flows is a plus. Full time - Apr 13