| Job alert | Jobs 1 - 10 of 158 |
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Compiler Engineer
Efficient Computer
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Santa Clara, CA, 95053
... Experience with verilog, system verilog, or VHDL. Knowledge of computer architecture. About Efficient Corporation: Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses ... - May 04
RTL ASIC Design Engineer
Wipro
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Sunnyvale, CA, 94087
... · Expertise in Verilog & System Verilog is a must. · Experience in Synthesis / Understanding of timing concepts for ASIC is required. · Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus. · Hands on ... - May 04
Modeling Engineer
The Judge Group
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Sunnyvale, CA, 94087
... Extremely strong in system Verilog and VCS. 4. Diligent and ensure first-pass success for models. a. Very disciplined and methodical. - Apr 21
SoC Integration Engineer - Onsite
Experis
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Sunnyvale, CA, 94088
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 01
Zebu Emulation
The Judge Group
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Sunnyvale, CA, 94087
... Following skills are very important: PCIe knowledge Expertise in controlling zTop Build/zCore Build (parts of ZeBu flow) Debugging failing FPGAs Extremely strong in system Verilog and VCS. Diligent and ensure first-pass success for models. Very ... - Apr 21
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Senior DFT Engineer - All levels
Oho Group Ltd
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Mountain View, CA, 94039
... and structural debug concepts and methodologies, including JTAG, IEEE1500, MBIST, scan dump, and memory dump Proficiency in Verilog, experience with simulators, and waveform debugging tools Knowledge of Verilog/SystemVerilog Familiarity with Python, ... - Apr 27
Design Verification Engineer
Intelliswift Software
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San Jose, CA
Design Verification Engineer - Remote / San Jose, CA Duration – 6 months + (can be extended longer) San Jose, CA / Remote Design Verification Engineer UVM System Verilog Test Bench Development SystemC (preferred) strong C/C++ - Apr 26
Senior Physical Design Engineer
Mirafra Technologies
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San Jose, CA
... and Verilog to collaborate with RTL and IP design teams for timing fixes • Contribute to timing flow and methodology improvements Key Challenges: • Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs. ... - May 08