| Job alert | Jobs 41 - 50 of 142 |
Senior Staff Digital Verification Engineer
Alpha & Omega Semiconductor
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Sunnyvale, CA, 94085
... test writing and verification of several products Experience with using the Cadence Virtuoso software and AMS simulation environment Comfortable with exploring the analog schematic hierarchy in Cadence Able to write and debug System Verilog models. ... - May 01
Analog IC Design Engineer
Unreal Staffing, Inc
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San Jose, CA
... transistor operation, and IC fabrication processes Experience with mixed-signal simulation and verification tools, such as Verilog-A, Verilog-AMS, or SystemVerilog for AMS Strong analytical and problem-solving skills, with the ability to analyze ... - May 01
Senior Design Verification Engineer
Capgemini Engineering
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Santa Clara, CA, 95053
... Position - Senior Design Verification Engineer Location - Santa Clara CA Full Time role with Capgemini Engineering Job description: We are looking for Senior Design Verification Engineer Key responsibilities: Proficient in System Verilog assertions ... - Apr 25
SoC Design Engineer
Omnivision Technologies, Inc.
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Santa Clara, CA
... Qualifications Minimum MSEE, or equivalent OR BSEE, or equivalent, plus 2 years of digital design experience Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of ... - Apr 12
RTL Design Engineer
Advanced Micro Devices, Inc
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San Jose, CA
... Design of digital circuits and components using Verilog/System Verilog Debugging in digital and mixed-signal simulation environment. Power-optimization of digital designs. Multi-clock domain designs. Design constraints for synthesis and static ... - Apr 30
RTL Design Engineer - Senior (US)
Managed Staffing
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Santa Clara, CA, 95054
JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for ... - Apr 24
Analog IC Design Engineer
Unreal Gigs
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San Jose, CA
... Experience with mixed-signal simulation and verification tools, such as Verilog-A, Verilog-AMS, or SystemVerilog for AMS. Strong analytical and problem-solving skills, with the ability to analyze complex circuit behavior and troubleshoot design ... - Apr 23
Verification Engineer/ASIC RTL / SoC Design Engineer
TetraMem - Accelerate The World
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Fremont, CA, 94537
... Pay Range: $110,000 - $250,000 ASIC RTL/SoC Design Engineer Requirements: ● MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design ● Experience with Verilog and system Verilog ● Experience with VCS, ... - Apr 29
Senior RTL Design Engineer
Protingent
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Santa Clara, CA, 95054
... Job Qualifications: • Bachelor's or Master's in Computer Engineering • 10 years' experience in RTL coding • Knowledge of PCIe Gen5 and PIPE specification • Knowledge of ASIC development flows • Knowledge of system verilog • Multi-clock domain ... - Apr 16
Principal Mixed-Signal Analog Design Engineer
Rambus
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San Jose, CA
... Prior design experience in FinFET process and digitally assisted design is desirable Experience in modeling with matlab, Verilog-A, verilog is desirable Experience working in leading R&D and future technology development projects is desirable The ... - Apr 23