| Job alert | Jobs 31 - 40 of 144 |
SoC Integration Engineer - Onsite
Experis
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Sunnyvale, CA, 94088
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 01
Eng Sr Prin II - Elec
BAE Systems
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San Jose, CA, 95112
... Defining detailed test plan and implementing Verilog simulation testcases to verify design functionality. Debug product, test and resolve design issues on hardware platforms Define hardware and firmware interfaces, protocols for circuits. ... - Apr 09
Integrated Circuit Design Engineer
Unreal Gigs
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San Jose, CA
... Strong understanding of digital design, RTL synthesis, Verilog AMS, SystemVerilog, and familiarity with analog circuit blocks and device physics. Benefits Competitive salary with potential for bonuses based on performance. Comprehensive benefits ... - Apr 23
Integrated Circuit Design Engineer
Unreal Staffing, Inc
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San Jose, CA
... (IC) Design Experience: Minimum 8+ years of experience in IC Design with a solid understanding of analog and digital design, Verilog, and familiarity with device physics Benefits Competitive salary with potential for bonuses based on performance ... - May 01
Integrated Circuit Design Engineer
Unreal Staffing, Inc
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San Jose, CA
... with some experience in high voltage AC/DC technical aspects preferred Strong understanding of digital design, RTL synthesis, Verilog AMS, SystemVerilog, and familiarity with analog circuit blocks and device physics Benefits Competitive salary with ... - May 01
Senior Hardware Security Architect
NVIDIA
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Santa Clara, CA, 95051
... Proficiency in Verilog RTL coding and scripting languages, such as: Perl, Python and Make etc. A working understanding of floor-planning, ASIC physical design, VLSI and DFT. A hands on technical background; excellent C programming and low-level ... - May 02
RTL Design Engineer
Protingent
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Santa Clara, CA, 95054
... Project Description: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible ... - Apr 30
Senior ASIC Design Engineer - Memory Controller
NVIDIA
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Santa Clara, CA, 95051
... Strong working knowledge of Verilog or VHDL. Experience with high speed clocking, cache interfaces and protocols. Familiarity with board and system level issues. Programming skills in C and/or PERL. Good communication skills and interpersonal skills ... - May 02
CIRCUIT DESIGN ENGINEER
Experis
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Santa Clara, CA, 95054
... • Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python. • Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like) • Proficiency in scripting languages like ... - May 02
Senior Mixed Signal Design Engineer
NVIDIA
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Santa Clara, CA, 95051
... or MS degree in Electrical Engineering or equivalent experience 5+ years of experience working in high-speed I/O digital design, knowledge at protocol level (SATA, PCIE, USB) preferred Have a deep understanding of Verilog or SystemVerilog, logic ... - May 02