| Job alert | Jobs 11 - 20 of 140 |
Verification Hardware Design Expert/Engineer (Onsite)
SEDAA
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San Jose, CA
... Desired Qualifications: Verilog Perl Scripting CAD Tools - May 01
Software Engineer (379555)
Placement Services USA, Inc.
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Palo Alto, CA
$126,984 per year
... create the Universal Verification Methodology (UVM) testbench that is written in System Verilog to verify the functionality and performance of the chip; examine the interrupt, register access, and Direct Memory Access (DMA) functionality in a full ... - Apr 22
Sr Design Verification Engineers GPU
Mirafra Technologies
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San Jose, CA
... • Code Functional coverage models and System Verilog assertions. • Drive Functional Coverage and Code coverage to closure. • Integrate C++ reference model into Scoreboards Requirements • 5-15 year’s industry experience in a design verification role. ... - Apr 20
Accelerator Verification Engineer
Ursus, Inc.
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Santa Clara, CA, 95053
... Expertise in System Verilog / C++ / Python . Ability to work in a fast paced environment and deliver results. - Apr 14
Zebu Emulation
The Judge Group
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Sunnyvale, CA, 94087
... Following skills are very important: PCIe knowledge Expertise in controlling zTop Build/zCore Build (parts of ZeBu flow) Debugging failing FPGAs Extremely strong in system Verilog and VCS. Diligent and ensure first-pass success for models. Very ... - Apr 21
RTL Design Engineer
LanceSoft, Inc.
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San Jose, CA
... PREFERRED EXPERIENCE: • 10 years' experience in RTL coding • Knowledge of PCIe Gen5 and PIPE specification • Knowledge of ASIC development flows • Knowledge of system verilog • Multi-clock domain designs. • Design constraints for synthesis and ... - Apr 17
Design Verification Engineer
OPENEDGES Technology, Inc.
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San Jose, CA
... based tracking methods to acquire and track coverage to closure Hands-on debugging simulation fails down to root-cause (Verilog RTL) Demonstrating good communication skills, works well in small dynamic teams Required Qualifications: The ideal DVE ... - Apr 20
FPGA Verification Engineer
Arista Networks
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Santa Clara, CA
... Job Responsibilities: Create and maintain test benches in Verilog/SystemVerilog Create BFM, RTL models for new and existing designs Develop the verification test plans and test cases Review the design functional coverage Concepts and Skills: Data ... - May 01
Design Verification Engineer
Mirafra Technologies
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Santa Clara, CA, 95053
... Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for ... - May 02
RTL Design Engineer - Senior
US Tech Solutions
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San Jose, CA
... Responsibilities: Knowledge of PCIe Gen5 and PIPE specification Knowledge of ASIC development flows Knowledge of system verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience: 10+ years of ... - Apr 10