| Job alert | Jobs 11 - 18 of 18 |
Design Eng 4 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... Advanced knowledge of System Verilog and UVM methodology. Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks. Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM ... - May 16
Field Programmable Gate Array Engineering Specialist
Baker Hughes
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Pune, Maharashtra, India
... Demonstrate good logic design concepts and computer design Be proficient in Verilog, VHDL and have had exposure to industry simulators Be able to build expertise in front end RTL design flow steps like lint, CDC, STA etc Work in a way that works for ... - May 12
Design Eng 5 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... Expertise in Verilog/VHDL and design implementation using FPGA development tools. Expertise in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as ... - Apr 23
ASIC Digital Design, Staff Engineer
Synopsys
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Chinchwad, Maharashtra, 411033, India
... Hands on experience with System Verilog, mythologies like VMM/UVM, simulation and debug tools. Experience with Version Control tools like Perforce/SVN. Knowledge of Perl/Shell scripts In addition, the candidate should have good communication skills, ... - Apr 30
ASIC Digital Design, Sr Engineer
Synopsys
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Tingre Nagar, Maharashtra, 411015, India
... Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Fundamental knowledge of Analog and ... - May 14
Eval Platform Tools and Infrastructure
Ethernovia
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Pune, Maharashtra, India
... Experience in Verification/validation experience including HW languages (System Verilog, Verilog, UVM) is a big plus. Experience in SystemC and transaction-level modelling (TLM). Soft Skills Self-motivated and able to work effectively both ... - Apr 26
Senior Engineer II - IP Verification
Alphawave Semi
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Pune, Maharashtra, India
... Minimum 5 years of experience in Verification Domain Experience in System Verilog and UVM. Expertise in Assertion-based verification and coverage closure. Good knowledge of scripting languages like, Python, Shell, and Make file. Should have worked ... - Apr 26
Design Eng 3 - LPQ
Lattice Semiconductor Corp.
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Shivaji Nagar, Maharashtra, 411016, India
... Advanced knowledge of System Verilog and UVM methodology. Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks. Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM ... - May 16