| Job alert | Jobs 51 - 60 of 121 |
Physical Design Engineer
Ambit Semiconductors Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Hands-on experience in STA of large blocks/Sub-systems or/and full chip Expert user of industry standard tools for timing signoff especially Synopsys PT. Expert in scripting languages (shell, perl, tcl) In-depth knowledge of 7nm/5nm/3nm technologies ... - Apr 26
DFT ENGINEER
GSVR Talent Solutions Pvt Ltd
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VasanthaNagar, Karnataka, 560001, India
... Actual Aware Synth Timing Closure SI Analysis Formal Verification Low-power Checks With a group of specialists in Physical Design, DFT Synthesis, and STA, ABC can give you a one-stop answer for building a wide range of cutting-edge authority items. ... - Apr 26
IO Circuit Design Engineer
HCLTech
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VasanthaNagar, Karnataka, 560001, India
... Responsibilities Design and implement various I/O circuits including: Buffers Level shifters Pads Clock drivers/receivers Termination resistors Integrate I/O blocks into the overall chip design Perform static timing analysis (STA) and ensure I/O ... - May 02
Senior SOC Physical Design Engineers
Samsung Semiconductor
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Bengaluru, Karnataka, India
... Complex SOC Top Physical Implementation for next generation SoCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs - Hands on experience doing ... - May 09
Senior Engineer, Digital Design Engineering
Analog Devices
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VasanthaNagar, Karnataka, 560001, India
... Work closely with physical design team for DFT implementation/constraints strategy for synthesis/STA. Analyze and debug test failures and collaborate with the test engineering team to resolve issues. Provide guidance and mentorship to junior DFT ... - May 12
SOC Timing Signoff Engineer
Intel
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Sadduguntepalya, Karnataka, 560029, India
Job Details: Job Description: We are looking for experienced STA engineer to drive the timing convergence of the high performance SoCs. Responsibilities include STA setup, convergence, reviews and sign-off for Multi-Mode and Multi-corner Multi ... - May 16
Staff Engineer, Digital Design
Analog Devices
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VasanthaNagar, Karnataka, 560001, India
... Deliver the DFT STA constraint to Physical Design team and ensure the timing closure of the DFT logic. Collaborate with the design team to ensure efficient and effective testability of complex integrated circuits. Design and implement DFT features ... - May 12
Lead Physical Design
SmartSoC Solutions Pvt Ltd
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Bengaluru, Karnataka, India
... • Must have done 5 to 8 tapeout with a successful track record of PnR & Sign off (STA, PV, EMIR). • Must have worked on lower node technologies : 3nm / 4nm / 5nm / 7nm • Must have good understanding of complex timing closure and low power ... - Apr 25
RTL Design Engineer
Eximietas Design
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Bengaluru, Karnataka, India
... Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. ... - May 17
Staff Application Engineer (Primelib / Library characterization)
Synopsys Inc
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Bengaluru, Karnataka, India
... Experience with commercial STA tools such as PrimeTime and simulation tools such as Hspice, Finesim is a strong plus. This is an exciting opportunity to be part of a fast-paced Applications Engineering team that is responsible for supporting and ... - May 16