| Job alert | Jobs 11 - 20 of 169 |
Senior Electrical Engineer
AOSense, Inc.
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Fremont, CA
... The control hardware for AO sensors spans a broad range of technologies including low-noise analog, low-jitter digital, rf/microwave, high voltage, microcontrollers, systems on a chip (SoCs), field-programmable gate arrays (FPGAs), and application ... - Apr 15
Design Verification Engineer
Park Lane Recruitment Ltd
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Milpitas, CA
... RESPONSIBLE FOR VERIFICATION OF ASIC DESIGNS INCLUDING: * Design Verification Implement test benches in UVM and System Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, ... - May 03
Non CDL Delivery Driver
Imperial Dade
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San Leandro, CA
... The driver will utilize a pallet jack, dolly, and lift gate to offload the merchandise and transport it to the customers. Imperial Dade is the leading independently owned and operated distributor of foodservice packaging and janitorial supplies in ... - May 04
Delivery Driver
Shastha Foods, Inc.
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San Jose, CA
... Experience in driving in local roads with frequent stops Operate lift gate, pallet jack and electric pallet jack Use of forklifts Company Description Shastha Foods, Inc., is a brand recognized in the Bay Area for over 21 years for its quality. ... - Apr 18
Senior ASIC Design Engineer
USA Tech Recruitment
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San Jose, CA
... Qualifications: 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V ... - Apr 25
DFT Engineer
Park Lane Recruitment Ltd
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Milpitas, CA
... * Strong knowledge of DFT methodologies, industrial standards, and practices * Strong working knowledge of Chip design, Verilog/System Verilog, and design verification * Experience with STA tools like Primetime, SDF generation and Gate-level ... - May 03
Principal Battery Design Engineer
Blue Current
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Hayward, CA, 94542
... to select best formulations and SOPs to meet performance and scalability goals * Drive quarterly cadence of updates and stage gate transitions * Internalize system design concepts (thermals, cell to pack) and compliance requirements from customers * ... - Apr 25
Design Verification Engineer
Mirafra Technologies
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Santa Clara, CA, 95053
... Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for ... - May 02
Maintenance Technician I
Sares Regis Operating Company, L.P.
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Fremont, CA
... • Works on external, as well as internal repairs which may include, but is not limited to, drywall repairs, painting, fence and gate repairs, plumbing installation or repairs, appliance repairs, boilers and HVAC systems, and common area clean-up. • ... - Apr 11
Silicon power benchmarking lab engineer
Intelliswift Software
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Sunnyvale, CA, 94087
... - Matlab, Python, Perl (or similar) scripting and data-post-processing tools - Excel for model fitting, data visualization and analysis - Diagnostic code development in C/C++ language - Experience with PTPX power flow and RTL/Gate simulation - May 03