| Distance: | Job alert | Jobs 1 - 10 of 30484 |
PCB Layout Engineer
Etched
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San Jose, CA
150000USD - 275000USD per year
... As a PCB Layout Engineer at Etched, you will play a crucial role in designing and optimizing printed circuit boards (PCBs) using Cadence Allegro PCB design tools. Your primary focus will be on high-speed signaling, including 100G applications, power ... - May 24
Staff Device Engineer
Power Integrations, Inc.
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Newark, NJ, 07175
... GaN power devices * Sound understanding of semiconductor device physics, especially WBG * Proficient in TCAD simulation and CADENCE layout tools * Hands-on experience with high-voltage testing and data acquisition systems * Strong communication and ... - May 21
Test Engineering Intern
Power Integrations, Inc.
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San Jose, CA, 95111
... * Learn Cadence HW developments tools. * Understand fundamentals of ATE testers, instruments, oscilloscopes and meters. * Learn how to apply C++ coding * Get trained in JIRA, Confluence and Bitbucket. * Develop Interpersonal and communications ... - May 19
Physical Design Engineer
Etched
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San Jose, CA
150000USD - 275000USD per year
... to GDSII sign-off Experience with back-end design and timing closure on advanced process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience with sign-off tools ... - May 24
Senior Director Analog IC Design
Lattice Semiconductor Corporation
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San Jose, CA, 95111
... * Experience designing circuits in advanced FinFET technologies * Proficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling * Lead and mentor a team of analog ... - May 23
Staff CAD Engineer
Aeonsemi, Inc.
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Santa Clara County, CA
... Developing Cadence Skill and/or python scripts that facilitate a design teams in processing design data. Maintain/Improve our python scripts for creating our project infrastructure, IP installations, backups, and support utilities. Job requirements ... - May 24
Senior Director Analog IC Design
Lattice Semiconductor Corporation
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San Jose, CA, 95111
... * Experience designing circuits in advanced FinFET technologies * Proficient in AMS design flows, tools, and methodologies like Cadence schematic capture, Virtuoso, Spectre, layout, and analog behavioral modeling * Lead and mentor a team of analog ... - May 21
Network Development Engineer
Voltai
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Palo Alto, CA
... We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign ... - May 24
Advanced Packaging SI/PI Engineer
Etched
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San Jose, CA
150000USD - 275000USD per year
... Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS. Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump ... - May 24
Power Electronics Engineer
Voltai
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Palo Alto, CA
... We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign ... - May 24