| Job alert | Jobs 1 - 10 of 139 |
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Modeling Engineer
The Judge Group
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Sunnyvale, CA, 94087
... Extremely strong in system Verilog and VCS. 4. Diligent and ensure first-pass success for models. a. Very disciplined and methodical. - Apr 21
SoC Integration Engineer - Onsite
Experis
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Sunnyvale, CA, 94088
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 01
Zebu Emulation
The Judge Group
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Sunnyvale, CA, 94087
... Following skills are very important: PCIe knowledge Expertise in controlling zTop Build/zCore Build (parts of ZeBu flow) Debugging failing FPGAs Extremely strong in system Verilog and VCS. Diligent and ensure first-pass success for models. Very ... - Apr 21
Senior DFT Engineer - All levels
Oho Group Ltd
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Mountain View, CA, 94039
... and structural debug concepts and methodologies, including JTAG, IEEE1500, MBIST, scan dump, and memory dump Proficiency in Verilog, experience with simulators, and waveform debugging tools Knowledge of Verilog/SystemVerilog Familiarity with Python, ... - Apr 27
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Design Verification Engineer
Intelliswift Software
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San Jose, CA
Design Verification Engineer - Remote / San Jose, CA Duration – 6 months + (can be extended longer) San Jose, CA / Remote Design Verification Engineer UVM System Verilog Test Bench Development SystemC (preferred) strong C/C++ - Apr 26
Software Engineer (379555)
Placement Services USA, Inc.
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Palo Alto, CA
$126,984 per year
... create the Universal Verification Methodology (UVM) testbench that is written in System Verilog to verify the functionality and performance of the chip; examine the interrupt, register access, and Direct Memory Access (DMA) functionality in a full ... - Apr 22
Senior ASIC Design Engineer
USA Tech Recruitment
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San Jose, CA
... Qualifications: 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V ... - Apr 25
SoC Integration Engineer - Onsite
Experis
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San Jose, CA
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 02