| Job alert | Jobs 1 - 10 of 255 |
RTL Design Engineer - Senior (US)
Experis
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Santa Clara, CA, 95054
Location: Onsite San Jose, CA JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified ... - May 02
Compiler Engineer
Efficient Computer
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Santa Clara, CA, 95053
... Experience with verilog, system verilog, or VHDL. Knowledge of computer architecture. About Efficient Corporation: Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses ... - May 04
Design Verification Engineer
Intelliswift Software
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San Jose, CA
Design Verification Engineer - Remote / San Jose, CA Duration – 6 months + (can be extended longer) San Jose, CA / Remote Design Verification Engineer UVM System Verilog Test Bench Development SystemC (preferred) strong C/C++ - Apr 26
SoC Integration Engineer - Strictly W2
Hire IT People, Inc
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San Jose, CA
... Half the team exposed to UVM and basic to good UVM working/debug background knowledge Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other ... - May 03
Senior ASIC Design Engineer
USA Tech Recruitment
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San Jose, CA
... Qualifications: 5+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V ... - Apr 25
ASIC Verification Engineer -RTL logic Design
European Recruitment
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San Jose, CA
ASIC Verification Engineer- System Verilog / UVM /RTL logic Design We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification ... - May 04
DFT (Design For Test) Engineer
Centraprise
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San Jose, CA
... Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST Verification skills include System Verilog Logic Equivalency checking and validating the Test-timing of the design. Experience working with ... - May 04
Sr. ASIC Design Engineer
ScaleFlux
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San Jose, CA
... Electrical Engineering or Computer Engineering with industry experience Proven experience of Verilog, System Verilog and C programming Knowledge of DSP algorithm including AES, Hash, ECC codec, data compression is a big plus Knowledge of Embedded ... - Apr 21
RTL Design Engineer - Senior
TekWissen ®
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Santa Clara, CA, 95053
... JOB Description: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for ... - May 04
Hardware Design Engineer
Sedaa Corp
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San Jose, CA
... Desired Qualifications: Verilog Perl Scripting CAD Tools Job title - Lab Hardware Engineer (Lab Work) Location - San Jose (onsite) The position involves candidate working in Client's Lab, participation and contribution in all phases of hardware ... - Apr 30