| Job alert | Jobs 1 - 10 of 19 |
COC HEAD - Electrical
Piaggio Vehicles Pvt. Ltd.
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Pune, Maharashtra, India
... Verilog, System Verilog, RTL, Digital Design. Work Experience Total 15-18 years of experience in the industry - Apr 21
ASIC Digital Design, Staff Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Fundamental knowledge of Analog and ... - Apr 18
Senior FPGA Design Engineer
Tudip Technologies
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Pune, Maharashtra, India
... Implement RTL code for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency. Collaborate with cross-functional teams including hardware engineers, software engineers, and system architects to define system ... - Apr 03
Design Engineer II
Cadence
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Pune, Maharashtra, India
... Location : Pune Design Engineer II Experience in developing complex test bench in System Verilog using OVM/UVM methodology Experience in coding functional coverage and system verilog assertions. Experience validation of protocols such as AXI4, AHB, ... - Apr 05
Mixed Signal Design Engineer
VASBEAM Private Limited
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Pune, Maharashtra, India
... Proficiency in system and behavioral modeling using MATLAB, System Verilog, Verilog-A/AMS. Desired familiarity with HDL languages Verilog and/or VHDL. Proficient in scripting languages such as Python, Perl, and C; additional skills are a plus. ... - Apr 12
Embedded Developer - C/C++
Acclivis Technology
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Pune, Maharashtra, India
... Experience in working with Hardware description languages such as VHDL or Verilog. Experience for developing for Hardware IP. Full time - Apr 18
ASIC Digital Design, Principal Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning,behavioralmodelling, and verification coverage metrics (functional coverage and code coverage) Identify design problems, ... - Apr 13
ASIC Digital Design, Staff Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... Requirements: Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas: - Must have experience in developing HVL (System Verilog) based test environments, developing, and ... - Apr 13
ASIC Digital Design, Staff Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Fundamental knowledge of Analog and ... - Apr 13
ASIC Digital Design, Sr Staff Engineer
Synopsys India Private Limited
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Pune, Maharashtra, India
... Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog Experience with System Verilog Assertions, code and functional coverage implementation and review Fundamental knowledge of Analog and ... - Apr 26