| Job alert | Jobs 21 - 30 of 441 |
ASIC/ SOC/ IP Verification 3 to in Bangalore / Hyderabad
Capgemini Engineering
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Bengaluru, Karnataka, India
... Primary Skills Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl. Secondary Skills Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, ... - Apr 25
Staff Design Verification Engineer
Renesas Electronics
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VasanthaNagar, Karnataka, 560001, India
... Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (OVM, UVM). Must be proficient in Verilog (System Verilog preferred). Understanding or prior experience with ... - Apr 10
Verification Lead
Mirafra Technologies
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Bengaluru, Karnataka, India
... What we are looking for : BE/MTECH with 5+ years of experience Languages: Verilog, System Verilog Methodology: UVM (preferred), OVM, VMM. Knowledge of scripting (Perl, C-shell) SVA will be a plus Good general verification experience with good ... - Apr 25
Trained Freshers RTL, Verification, PD, DFT
Cerium Systems Pvt. Ltd
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VasanthaNagar, Karnataka, 560001, India
Develop and implement RTL designs for digital circuits and systems Collaborate with cross-functional teams to understand design specifications Utilize hardware description languages (Verilog/VHDL) for RTL coding Perform synthesis and optimization to ... - Apr 18
ASIC Engineer, Implementation
Meta
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Bengaluru, Karnataka, India
... Experience Knowledge of RTL coding using Verilog/System Verilog. Experience with Timing/physical libraries, SRAM Memories. Experience with Power, Performance, Area Analysis and techniques for reducing power. Experience with Clock Domain Crossing, ... - Apr 17
Applications Engineering, Staff Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Understanding of Verification concepts and writing test benches Should have very good hands on experience in Verilog and/or VHDL. Proven problem solving skills. Should have good experience in Synthesis, back end flow, FPGA architecture and ... - Apr 18
Senior Design Verification Engineer
ACL Digital
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VasanthaNagar, Karnataka, 560001, India
... verification Hands on experience with assembly, UVM, SV, C++ Experience in developing complex test bench/model in UVM, Verilog, System Verilog Hands on experience in developing test plans, coverage closure Ability to code readable, maintainable ... - Mar 31
R&D Engineering, Staff Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... He should be expert in C/C++ and have understanding of compiler and HDLs (Verilog/System Verilog). We need people with at least 7 years of experience in some EDA technology. Full time - Apr 13
Design Verification Engineer
Zigsaw
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Sadduguntepalya, Karnataka, 560029, India
₹100000.000 - ₹150000.000 per annum
... Key Qualification BS/MS in EE/EC with 7+ years of relevant experience in the verification of IP cores and/or SOC Must have proven experience in developing HVL (System Verilog/UVM) based test environments developing and implementing test plans ... - Apr 03
Snr Design Verification Engineer
Tech Mahindra
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VasanthaNagar, Karnataka, 560001, India
Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs ... - Apr 19