| Job alert | Jobs 1 - 10 of 43 |
SAP CDC-CIAM Architect
viraaj hr solutions
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Bengaluru, Karnataka, India
INR 1000000.000 - INR 2500000.000 per annum
Overview: The SAP CDC-CIAM Architect plays a crucial role in designing, implementing, and supporting SAP Customer Data Cloud (CDC) and Customer Identity and Access Management (CIAM) solutions within the organization. They are responsible for ... - Sep 12
ASIC Engineer, Design
Meta
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Bengaluru, Karnataka, India
... Responsibilities: ASIC Engineer, Design Responsibilities: Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, selection and integration ... - Aug 28
ASIC Engineer, Implementation
Meta
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Bengaluru, Karnataka, India
... We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ... - Sep 02
PD - Frontend Synthesis
Wipro
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Bengaluru, Karnataka, India
... Fullchip rollup, Synthesis, Front end /Back end interactions, CDC, PAD IOs, Package design Fullchip timing - PrimeTime constraints, clocks. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains. ... - Sep 07
ASIC Engineer, Design
Meta
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Bengaluru, Karnataka, India
... Responsibilities: ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Lint, CDC, Synthesis, & Power Optimization Soft and hard IP identification, ... - Sep 01
Data Engineer
Magna
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Bengaluru, Karnataka, India
... • Models Database objects to fulfil data pipeline requirements • Designs following integrations: o ETL jobs using incremental load patterns, using technologies like Change Data Capture (CDC) or Change Tracking o Services for APIs using technologies ... - Aug 23
ASIC RTL Design Leads
Wipro
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Bengaluru, Karnataka, India
... * In depth knowledge on RTL quality checks (Lint, CDC). * Knowledge of synthesis and low power is a plus. * Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). * Good understanding of timing concepts. * Knowledge of one or more of the ... - Sep 07
RTL Engineer and Design Verification engineer
Tessolve
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Bengaluru, Karnataka, India
... Exp: 8+ yr exp Skills: RTL ASIC, CDC, Lint, Synthesis, Spyglass . Design verification engineer : Exp: 3 to 20 yrs Location : PAN INDIA • IP verification Using SV/UVM • SOC Verification using C/SV • Third Party VIP Integration • Interconnect ... - Sep 18
RTL Design Engineer
Wipro
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Bengaluru, Karnataka, India
... In depth knowledge on RTL quality checks (Lint, CDC). Knowledge of synthesis and low power is a plus. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Good understanding of timing concepts. Knowledge of one or more of the interface ... - Sep 07
Senior ASIC RTL Lead
Wipro
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Bengaluru, Karnataka, India
... About the Role: Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus ... - Sep 07