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Physical Design Lead
TekWissen India
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Visakhapatnam, Andhra Pradesh, India
... integration • Power grid creation • Low power design Signoff checks • LEC ( conformal) • RV (ansys) • LV (drc clean up – caliber) • PTPX • VCLP (vc static checks) • Caliberlite (intel internal) • Timing closure (PT ECO/ Tweaker) • ESD runs Full time - May 02