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ASIC, FPGA, SoC - Design and Verification Engineers
Steinman Recruiting Associates
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Boston, MA, 02115
$130000 - $190000 / yr
... Front-end Digital Systems Design (Senior – Principal): Fluent in SystemVerilog, Verilog or VHDL and familiar with LINT. Architectures for Secure systems design. Tape-outs at advanced nodes. You will develop the architecture, designs circuits and/or ... - Jul 09
Senior Control System Engineer
Voyant Photonics
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Manhattan, NY, 10018
... Strong understanding of FPGA design using MATLAB Simulink and Verilog or VHDL coding. Ability to collaborate with hardware engineers to implement, bring up, and test mixed-signal circuits. Excellent analytical and troubleshooting skills to diagnose ... - Jul 18
FPGA Engineer
Jane Street
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New York, NY
... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in ... - Jul 10
FPGA Engineer
Jane Street
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London, Greater London, United Kingdom
... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing/integration, but you can also expect to work with some Verilog and C. While you don’t need to have worked with OCaml specifically, a good background in ... - Jul 10
RTL Design Engineer
Apple
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San Diego, CA
$139,500-$258,100/year
... Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Validated knowledge of synthesis, static timing, DFT, is a plus ... - Jul 06
Mixed Signal Circuit Design Engineer
Apple
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Waltham, MA
$162,500-$286,400/year
... Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design team. Solid understanding of Circuit Verification tools (Simulators, Extraction, EMIR, Noise, SigEM, etc.). Generate block/chip level ... - Jul 06
CAD Engineer - RTL Construction
Apple
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Beaverton, OR
... Minimum requirement of Bachelors Degree +3 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 03
CAD Engineer - RTL Construction
Apple
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San Diego, CA
$139,500-$258,100/year
... Minimum requirement of Bachelors Degree +3 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 06
ASIC Engineer Remote )
TalentPro Consulting
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Baltimore, MD
$65.00 - $90.00
... • Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies. • Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals. Basic ... - Jul 16
Cellular ASIC Design Integration Engineer
Apple
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Sunnyvale, CA
$126,800-$190,900/year
... Knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.) Analytical skills to be able to make design tradeoffs for best performance, low area, and low power. Knowledge of power analysis tools/flows and UPF flow for defining power ... - Jul 06